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Aldec integrates Altera HDL support in simulator

Posted: 10 May 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Aldec? mixed-language? simulator? design tool? ASIC?

Aldec Inc., a provider of mixed-language simulation and advanced design tools for ASIC and FPGA devices, announced that its simulator now has integrated HDL support from Altera's Quartus II version 6.0 development software environment.

According to the press release, mutual customers can now select Aldec's HDL Simulator, Active-HDL, directly from Altera's Quartus II software version 6.0. The interface provides customers with the ability to specify the format and location of functional and timing simulation files in Quartus II software version 6.0. The integration provides mutual customers with a seamless interface to Active-HDL for quick HDL simulation set-up to support the increasingly large and more complex FPGA devices being delivered from Altera.

"With the continued growth of our customer base in the FPGA market and Altera's ever increasing device capacity, the natural progression was product integration to provide our mutual customers with greater productivity," said Dave Rinehart, vice president of marketing at Aldec. "The complexity of FPGA designs continues to rise and the integration of Aldec's core technology in HDL simulation combined with the Altera's design tools provides customers with an even faster track to their simulation results."

Jim Smith, Altera's director of EDA relations, said that its Quartus II software delivers a robust and comprehensive programmable logic and structured ASIC design flow. "Providing an interface to Aldec's popular Active-HDL simulator will enable our mutual customers to achieve even tighter integration between Aldec's tool and our development environmentmaking our customers' jobs easier with a seamless debugging solution," Smith said.

Already available, the interface is a standard feature in both Aldec's Active-HDL and Altera's Quartus II environments.

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