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PLD tool gets upgrade

Posted: 10 May 2006 ?? ?Print Version ?Bookmark and Share

Keywords:ispLEVER? programmable logic design? Lattice Semiconductor? FPGA?

Lattice Semiconductor Corp. announced the availability of its ispLEVER 6.0 programmable logic design tool suite, which supports the 90nm LatticeECP2 and LatticeSC FPGAs. Features offered by the 6.0 release include support for 90nm FPGAs, the introduction of a new Design Planner interface, support for schematic FPGA design and an expanded library of IPexpress user-configurable IP cores.

The Design Planner integrates the optimization tools Preference Editor and Floorplanner. The Preference Editor is used to define design parameters such as critical paths and timing objectives, which, because they are by definition device-specific, cannot be specified at the hardware description language level. The Floorplanner supports control of logic placement within a device.

The new IPexpress flow aims to reduce design time by allowing IP parameterization and timing analysis on the designer's desktop. It allows designers to simulate, place and route, generate netlists and run static timing analysis with their own logic and selected core parameters in real-time. IPexpress-supported functions include DDR, Ethernet, FIR, FFT, PCI and Reed-Solomon encoder and decoder. Lattice said it intends to make several more IPexpress cores available throughout the year.

Included in the ispLEVER design suite are Mentor Graphics' Precision RTL synthesis version 2005c and ModelSim simulator version 6.1d, and Synplicity's Synplify synthesis version 8.5d.

The new version comes with a schematic design library for the ispLEVER Schematic Editor, which is intended to assist designers in developing gate-level circuits based on library elements from the ispLEVER FPGA Libraries Help System. The libraries contain standard Boolean gates, latches, flip-flops and I/O buffers compatible with Lattice FPGA device families. A new tutorial included in ispLEVER 6.0 provides design examples using a mixture of gate-level schematics modules generated by IPexpress, and RTL blocks to complete a design with the Schematic Editor.

The new Lattice FPGA schematic library supports the LatticeECP2, LatticeECP/LatticeEC, LatticeSC, LatticeXP and MachXO families.

The ispLEVER 6.0 software for Windows, supporting all Lattice digital programmable logic families, is priced at $695. Unix and Linux versions also are available.




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