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Japan extends chip R&D

Posted: 16 May 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Yoshiko Hara? Asuka? 65nm? 45nm? 32nm?

A new five-year effort to build chips in geometries as fine as 32nm is under way in Japan, a trade group backing the R&D said recently.

Extending a project begun in 2001 to shore up Japan's competitiveness in the world semiconductor market, Asuka II will spend more than $150 million annually to develop cutting-edge chips in 65nm, 45nm and, by 2011, 32nm processes.

Starting last month, the Japan Semiconductor Industry Association's (JSIA) Asuka II project will run until March 2011, with a total budget of about $767 million for the five years. Under the JSIA's control, Asuka II comprises R&D conducted at the Semiconductor Technology Academic Research Center (Starc) and at Semiconductor Leading Edge Technologies Inc. (Selete).

R&D companies Selete and Starc were founded by Japanese chipmakers Fujitsu, Matsushita Electric Industrial, NEC Electronics, Oki Electric Industry, Renesas Technology, Rohm, Sanyo Electric, Seiko Epson, Sharp, Sony and Toshiba. These companies form the JSIA, an organization within the Japan Electronics and Information Technology Industries Association.

In Asuka II, Starc will pursue design methodology, with a five-year budget of about $170 million. Starc's advanced program targets SoC development for 65nm by 2008 and 45nm by 2011, especially focusing on design-for-manufacturability. Selete, for its part, will develop advanced processes and devices, funded by a total budget of about $596 million. Core members will focus on implementing technologies for 45nm and 32nm, such as high-k, low-k/copper, extreme-ultraviolet (EUV) lithography and mask technologies for EUV.

While the original Asuka effort brought all of Selete's and Starc's member companies into each program, the project's latest extension involves only core membersFujitsu, NEC Electronics, Renesas and Toshibain all programs. Other companies will join some programs depending on their interests.

Selete joins with Starc to create the Asuka II project, but separately, it also forms the Tsukuba Semiconductor Consortium with the Mirai project, a research operation organized by the National Institute of Advanced Industrial Science and Technology and the Association of Super-Advanced Electronics Technologies. Selete and the Mirai team are both developing semiconductor technologies at the same Super Clean Room in Tsukuba, about 30miles northeast of Tokyo, but they occupy separate working areas because Selete represents the private sector and Mirai is government-sponsored.

In the first phase of Asuka and Mirai in early 2000, Asuka focused on technologies of 90nm to 65nm, closer to practical applications, and Mirai on more-futuristic technology of the 45nm generation. The two teams were often criticized for not cooperating effectively.

Taking this criticism into consideration, the Semiconductor Industry Research Institute Japan (SIRIJ), which set the ground rules for these R&D efforts, said a project leader will be named for Asuka II, with R&D projects to be conducted under the leader's direction. But in practice, the leader's position seems to have lost ground.

In the new R&D system, Selete and Mirai form a virtual consortium named Tsukuba Semiconductor Consortium (TSC) under a leader described as the "TSC linkage supervising leader."

"Each project has its leader," said Kenji Maeguchi, executive director of SIRIJ. "The TSC linkage leader does not step into the content of each project, but he helps to avoid overlapping and to urge the implementation of developed technologies into practical applications."

Hisatsune Watanabe, Selete's president, has been named TSC leader. He has vowed to broaden input at the top, saying the information should reflect more than the views of upper management. "So, I am going to expand the involvement to lower-level leaders to exchange information."

In the first phase, Selete and Mirai teams took different approaches in technologies like high-k and low-k. "We agreed to take over Mirai's ideas and will merge such ideas with those of Selete," said Watanabe. The Mirai project will continue exploring more futuristic technologies such as a new CMOS structure.

"It does not mean that the leader moves projects," said Satoru Ito, president and CEO of Renesas Technology and acting JSIA chairman, "but we can expect closer linkage than before."

- Yoshiko Hara
EE Times

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