Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Controls/MCUs
?
?
Controls/MCUs??

Rethinking embedded flash memory choices

Posted: 16 May 2006 ?? ?Print Version ?Bookmark and Share

Keywords:don barnetson? samsung? samsung semiconductor? embedded? spotlight?

New requirements of the marketplace!especially in many consumer embedded designs and mobile devices!mean that we should rethink our priorities about non-volatile memory and look for new alternatives.

In recent years, NAND flash memory architecture has become the predominant memory type applied in CE due to its data storage and retrieval capabilities.

NOR flash memory was designed for code execution!the so-called, execute-in-place (XiP) model. However, as products have evolved!especially mobile consumer devices!NOR has been tasked with storing limited amounts of data as well, although it is handicapped by slow write speeds and high cost. The NAND architecture was developed specifically with data applications in mind. NAND flash inherently enables fast write speeds and the construction of much denser non-volatile memory at a much lower cost-per-bit than NOR flash.

But with new application requirements in many embedded systems, especially CE, there is a growing need for converged architectures combining the capabilities of both.

Direct XiP capability, an SRAM-like interface, read bandwidth of up to 108MBps and random accessibility made NOR flash ubiquitous in voice-centric handsets. The multiplexed interface of NAND flash memories was not built into the controllers or processors of the time, which limited NAND flash to dedicated applications.

When considered as data-centric memory, NAND provides several distinct advantages over NOR as a storage medium, including faster write speed, much lower cost-per-bit and increased reliability. NAND can be written at 17MBps!about 100 times faster than can a comparable multilevel-cell NOR device. NAND is roughly 40 percent less expensive in cost-per-bit than NOR at similar densities and NAND can be scaled to 4Gbit in a single device, while NOR has not exceeded 1Gbit.

Finally, from a reliability standpoint, NAND implementations have built-in error correction protocols and bad-block management similar to HDDs. NOR, as a directly addressable memory, has no provisions to handle errors. A bad bit in NAND can be handled transparently to a user, but a bad bit in NOR can result in a costly system crash or time-consuming file corruption.

New combinations
As more functions (e.g. cameras and MP3 audio) have been added to handsets and sophisticated operating systems (e.g. Symbian, Linux and Windows Mobile) have been used, the need for data storage has increased so much that a third memory!a NAND flash device!became necessary to hold data.

Moreover, the amount of volatile memory and bandwidth requirements grew so much that SRAM or PSRAM has been replaced by a mobile DRAM that has up to 10x the bandwidth and much lower cost-per-bit than SRAM or PSRAM. Consequently, the OS has increasingly taken advantage of that bandwidth and, instead of being executed from the NOR device, moves its code-base into DRAM on power-up in a store-and-download (SnD) approach.

In that memory model, the NOR device is used primarily for booting at power-up; the lower-cost NAND device is used for storage; and the DRAM is used for executing data applications, buffering and other high-speed tasks.

Some designers questioned why so much budget should be devoted to an XiP-capable NOR device when it is used only to boot a system. Chipset companies have responded and added bootable NAND controllers to their products!enabling for the first time a NOR-less system, with the NAND device handling both the code and data functions required by the handset.

Demand paging
The memory model of a pure NAND + DRAM play is increasingly applied. In that model, the code base is transferred from NAND to DRAM on power-up and executes from DRAM while in use. However, some designers wonder why the entire code base must be transferred to DRAM, when portions needed at any given moment could be transferred, reducing the size of the DRAM required. Given that challenge, a new model is gaining favor!demand paging.

Demand paging has been used in PCs for many years to allow the hard drive to supplement the amount of installed DRAM, as needed. Assuming that the desired pages of code can be summoned quickly when necessary, the entire demand-paging process can be transparent to the end-user, substantially reducing the DRAM required and translating to significant savings in materials.

Using a demand-paging approach, the key to performance efficiency is how quickly a page can be read from the NAND memory into DRAM. The ideal flash solution would have the read bandwidth of NOR flash (108MBps) and the write speed and low cost of a NAND device. To meet that objective, converged flash/SRAM fusion architectures such as OneNAND from Samsung have begun to emerge.

Memory fusion
One of a number of new converged flash device architectures being proposed, OneNAND, has a NAND flash array at its core, but adds logic and SRAM buffers to map the NAND flash to a NOR interface. The device can be read at NOR speeds and can be written at NAND speeds while maintaining NAND's low-cost structure.

In addition, error correction logic is built into the device. It has an SRAM-mapped boot RAM, so that systems without a NAND interface can seamlessly connect to such devices. As a NAND-NOR-SRAM fusion memory, it is designed to satisfy the needs of a demand-paging environment in next-generation handsets.

The core NAND architecture is transparent to the application processor, which can issue a command to load a page from the NAND array to the SRAM buffer, then read that page via the NOR interface. This process happens automatically on power-up for the first 1Kbyte of code, which becomes available for booting via the 1Kbyte BootRAM memory mapped to the fusion architecture's base address. By doing this, it can be used as the unified flash solution for any processor with an SRAM interface.

NOR flash memory has become less practical to use than NAND flash memory in new generations of mobile products in which multimedia functions are the driver, although NOR will continue to be used in voice-centric handsets. However, a sharp rise in demand for NAND calls for greater care in planning by CE OEMs, embedded-systems designers and industrial-device designers, as applications grow more complex, use faster processors and have a greater need for memory.

- Don Barnetson
Associate Director, Flash Memory Marketing
Samsung Semiconductor Inc.




Article Comments - Rethinking embedded flash memory cho...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top