Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Aldec simulators validated for Lattice devices

Posted: 17 May 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Aldec? design tool? ASIC? FPGA? Lattice Semiconductor?

Aldec Inc., a supplier of mixed-language simulation and advanced design tools for ASIC and FPGA devices, announced that Lattice Semiconductor Corp. has validated Aldec's Riviera and Active-HDL simulators for use with Lattice devices. Mutual customers can now utilize Aldec's simulators in conjunction with Lattice's ispLEVER 6.0 design environment when implementing Lattice devices.

"Lattice's use of our simulator in the validation process of their libraries, including the newest 90nm devices, enables Aldec to fully support designers using the latest Lattice devices," said David Rinehart, vice president of marketing at Aldec, in a statement.

According to the press release, the ispLEVER 6.0 programmable logic design tool suite is a complete design environment for all Lattice digital FPGA devices. The addition of Aldec's simulation technology support in ispLEVER 6.0 allows mutual customers to utilize Aldec's HDL simulation technology as well as co-simulation support for Matlab and Simulink.

"The Lattice ispLEVER 6.0 design tool suite includes support for the industry's fastest 90nm FPGAs," said Tim Schnettler, director of design tools marketing at Lattice. "By validating our libraries at the factory using Aldec's simulation technology, we are able to provide our mutual customers with a synchronized release and the highest quality support."

Article Comments - Aldec simulators validated for Latti...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top