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Cadence tech supports TSMC's 65nm design

Posted: 19 May 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Cadence Design? TSMC? Taiwan Semiconductor Mfg Co.?

Cadence Design Systems Inc. announced that its device and interconnect models, design flows and design for manufacturing (DFM) technologies support Taiwan Semiconductor Mfg Co.'s (TSMC) 65nm technology.

According to the press release, Cadence can help shorten the design cycle, maximize first-pass silicon success, and address manufacturing issues throughout the design chain by providing designers an integrated methodology to address 65nm. "Lowering barriers for advanced design is critical to increasing the adoption rate for 65nm technology," said Edward Wan, senior director of design services marketing at TSMC. "We work with Cadence to achieve a faster ramp to volume by allowing designers to address manufacturing and lithography effects."

Technology files for Cadence QRC Extraction, as well as device models for the Cadence Virtuoso Spectre Circuit Simulator, are now available from TSMC and have been validated for TSMC's 65nm Nexsys process design rules. Cadence simulation technology has also been updated with the latest BSIM device models incorporating key 65nm effects on device characteristics, such as LOD/STI and well proximity, to enhance silicon-accurate results for designs using TSMC's 65nm Nexsys process.

The 65nm designs face complex issues, such as an exponential increase in leakage power, tight manufacturing parameters, and new extraction requirements. Both companies are continuing their design-chain collaboration to address these issues through comprehensive design kits and reference flows for TSMC's 65nm process.

"At advanced process nodes, designers face increasing impact from physical and lithographic effects that significantly degrade circuit performance and yield. By providing solutions that more accurately model 65nm manufacturing effects, we can help designers anticipate manufacturing and lithography-based concerns during the design process," commented James Miller, Jr., executive vice president for products and technologies organization at Cadence.

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