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Synopsys to distribute TSMC 65nm Nexsys libraries

Posted: 22 May 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Synopsys Inc.?

Synopsys Inc. was named by Taiwan Semiconductor Mfg Co. (TSMC) to distribute its production-ready, silicon-validated 65nm Nexsys standard cell libraries, I/Os and memory compilers through Synopsys' DesignWare IP library.

TSMC developed the libraries in close relationship with their process development teams to ensure conformance to its design-for-manufacturing rules. The libraries were validated through the TSMC-9000 program to meet their rigorous library quality criteria. Both companies also worked together to validate that the Nexsys libraries provide full support for the TSMC Reference Flow 6.0 within Synopsys Galaxy Design and Discovery Verification Platform.

TSMC Nexsys standard cell libraries offer a complete set of high-performance, high-density cells and include multiple voltage thresholds to enable power and speed trade-offs, the company said. Nexsys libraries also enable low power design and mitigating power leakage by supporting Power Gating and Voltage Scaling design implementations.

Additionally, TSMC's I/Os offer unique features such as Circuit-Under-Pad, flip-chip support and staggered or linear bonding within one library. The company's memory compilers are optimized for low dynamic and leakage power. They include a single port SRAM with and without redundancy, dual port SRAM, a single-port and two-port Register File, and a ROM compiler.

"The TSMC Nexsys libraries are a key element in our broad portfolio of silicon-proven IP. Working with TSMC illustrates our commitment to provide essential IP to engineering teams worldwide for the development of their leading-edge SoC designs," said Guri Stark, vice president of marketing for the solutions group at Synopsys.




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