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TSMC speeds up 45nm intro

Posted: 22 May 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Mark LaPedus? Taiwan Semiconductor Manufacturing Co.? TSMC? 45nm process?

Taiwan Semiconductor Mfg Co. (TSMC) on recently disclosed some of the first details of its new and advanced 45nm process, with plans to accelerate the introduction of the offering in 2007.

The company, however, appears to have hit a brick wall with certain elements of the 45nm technology and will most likely push out the adoption of high-k gate dielectrics and metal gates from the 45nm node to the 32nm node, according to a company executive.

Initially, TSMC plans to release a low-power version of its 45nm process, followed by other variations of the technology, and move into "risk production" for the low-power, 45nm technology in Q4 of 2007. Now, the company has pulled in its introduction date and plans to move into "risk production" in Q3 of 2007, said Shang-Yi Chiang, senior VP of research and development, during a presentation at the company's technology forum.

TSMC's 45nm process is a 10-metal-layer technology, with gate lengths said to be down to 26nm, according to Chiang. The process itself is equipped with copper interconnects, strained silicon, triple-gate oxide and a second-generation low-k dielectric film.

In addition, the company is expected to insert 193nm immersion lithography tools for production at 45nm, Chiang said. TSMC is reportedly using 193nm immersion scanners from ASML Holding NV of the Netherlands.

At 45nm, the silicon foundry giant plans to deploy a low-k film with a "k factor" of 2.5-to-2.6, Chiang said. TSMC is using low-k films with a rating of 2.9-to-3 for its 90-to-65nm processes, based on Applied Materials Inc.'s Black Diamond-enabled chemical vapor deposition technology.

"We are still working on it," said Chang. He added that TSMC has not ruled out the use of high-k or metal gates at 45nm. Instead, the company will most likely continue to extend silicon dioxide or a variation of the technology at 45nm, pushing out high-k and metal gates at the 32nm node.

- Mark LaPedus
EE Times

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