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TSMC, UMC ready for 65nm X Architecture designs

Posted: 29 May 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Dylan McGrath? Taiwan Semiconductor Manufacturing Co.? United Microelectronics Corp.? TSMC? UMC?

Taiwan Semiconductor Manufacturing Co. Ltd (TSMC) and United Microelectronics Corp. (UMC) recently announced that they have validated Cadence Design Systems Inc.'s X Architecture for 65nm production.

The X Architecture is said to provide improvements in chip area, performance, power consumption and cost by enabling designs with shorter wirelengths and fewer vias.

"TSMC and Cadence have engaged with multiple customers for 0.13m, 0.11m and 90nm X Architecture production designs, and are now working with early customers targeting our 65nm process," said Ed Wan, senior director of TSMC's design services marketing, in a statement. TSMC said it is providing 65nm X Architecture design rules that allow customers to achieve lower cost, higher performance and lower power designs.

Both companies tout history with the X Architecture, an approach for orienting a chip's interconnect wires using diagonal routes in addition to traditional right-angle "Manhattan" routing, which was introduced in 2001. Last year, TSMC became the first foundry to produce an X Architecture device, a PCI-Express graphics processor from ATI Technologies Inc. UMC was the first pure-play foundry to join the X Initiative.

"UMC has been working with Cadence for several years to bring the advantages of the X Architecture to mainstream SoC designers," said Patrick Lin, chief SoC architect at UMC. "We are delighted to extend our readiness of this technology to the 65nm generation, as leading customers can now leverage the X Architecture with the industry's most advanced process technology to increase the competitiveness of their products."

Both companies say they are now production-ready for 130nm, 90nm and 65nm. TSMC also offers 110nm X Architecture capability.

- Dylan McGrath
EE Times




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