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ST unveils 'first' 90nm SoC for HDDs

Posted: 30 May 2006 ?? ?Print Version ?Bookmark and Share

Keywords:ST? 90nm? SoC? HDD? T90?

STMicroelectronics has announced its design and manufacturing capability for HDD SoC devices in 90nm technology. According to the company, its new devicewhich integrates ST's intellectual property in the hard disk controller, the read channel, serial ATA interface and memoryis the first such product to be manufactured in the 90nm process. Functional silicon is currently being evaluated and tested, and is sourced from Crolles2 Alliance 300mm wafer facility in Crolles, France.

ST's T90 read channel IP supports data rates ranging from 300Mbps to 1.7Gbps, and along with the serial ATA performance, said the company, makes this design suitable for the 2.5-inch and 3.5-inch disk drives used in high-end mobile, desktop computers and servers.

Read channels encode and decode data flowing between the head preamplifiers and the serial ATA interface and memory, demanding advanced mixed-signal technologies. This 90nm design is based on ST's Tintoretto read-write channel architecture, said the company, which enables high data rates while low power dissipation in all HDD operating modes.

The T90 supports 10bit high-rate codes and reverse order coding, media noise optimized data detection, advanced defect scan, longitudinal and perpendicular recording, and self servo write.

The embedded hard disk controller, which manages data flow and controls head positioning during track and seek operations, is based on ARM technology and features a 32bit CPU core running at 450MHz, said ST.

ST last year announced the fabrication of the Multi-Interface Physical Layer in 90nm. This macro-cell provides the serial ATA interface in the new chip and can also support applications using the serial attached SCSI, Fiber Channel, and PCI Express serial interface standards, enabling fast design validation for different markets and reducing costs for manufacturers by optimizing engineering resources, STsaid. The serial ATA interface is capable of 3Gbps and has shown jitter performance of less than 2ps random and less than 50ps total.

Roberto Fantechi, general manager of ST's Data Storage Division, said, "Now, with the first 90nm SoC to reach the market, we can offer our customers increased functionality in the same silicon space, as a result of the higher gate density, coupled with lower power requirement and cost."




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