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Startup enables IC variability characterization

Posted: 01 Jun 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Richard Goering? EE Times? Stratosphere Solutions Inc.? design-for-manufacturing? design-for-yield?

Numerous design-for-manufacturing (DFM) startups are promising to help designers maximize yields and manage process variability, but it all starts with the ability of silicon fabs to provide statistical parametric characterization. Stratosphere Solutions Inc. recently stepped forward to address that issue with intellectual property (IP) that inserts test structures in silicon wafers.

Stratosphere Solutions was launched in 2004 by Jim Bordelon, CTO, and Prashant Maniar, chief strategy officer. Both previously served at yield-management provider HPL Solutions before its 2005 acquisition by Synopsys Inc. EDA veteran Bob Smith, most recently the president and CEO of InTime Software, recently joined Stratosphere as chairman and chief executive.

"Our focus as a company is to solve the parametric variability problem," said Maniar. "What we are looking at is in-die variations

how do transistors, located on two different parts of the die, behave differently because of proximity effects, dopant fluctuations or line-edge roughness."

Other DFM and design-for-yield (DFY) companies, Maniar noted, focus on lithography simulation or on modeling chemical metal polishing. "What is missing is the type of data necessary to make all this successful," said Maniar. "If anybody is going to be successful with DFM or DFY, you've got to start with the fab."

Toward that end, Stratosphere Solutions rolled out StratoPro, a combination of IP and software that embeds test structures that fabs use to characterize process variability. The four-person company also has plans for a yield-modeling environment that will allow fabs to provide designers with comprehensive yield models without divulging trade secrets. That offering is expected around year's end.

There are two versions of StratoProa reticle version, in which large test structures are dropped onto a wafer, and a "scribe line" version, in which test structures are inserted in the scribe lines along which the wafer will be chopped up to produce individual chips. Although the scribe line metal is ultimately thrown away, fabs often place test structures in the scribe lines so as not to waste any metal.

For many fabless semiconductor companies, scribe line test structures are the primary source of information about device performance, Maniar noted. They could use the scribe line version of StratoPro to compare foundry information vs. what's actually measured on the wafer.

Fabs today already place test structures on wafers, but StratoPro claims its "Parametric ActiveMatrix" does so at 10 times the density. While traditional solutions require a set of pads for each transistor, StratoPro uses an addressable array with a common set of pads, Smith said. "Because you don't need a set of pads to reach each device, you get an order-of-magnitude more test structures in the same area," he said, providing "a much richer set of data about what's actually going on in the process."

The StratoPro test structures enable a full analog parametric set of measurements, Maniar said, including IV curves, threshold voltage, drive currents and gate voltage. "You may not be able to measure or characterize very low levels of leakage current," he said. "That's because you may have some leakage from the array itself."

StratoPro comes with test programs for Agilent testers, and Stratosphere is working on test programs for Keithley testers.

"There's always going to be random variability" in any process, Smith said. "You can't build a mathematical model. You have to go into that process, get a bunch of data points and build statistical curves that show how it's really behaving. We're giving the fabs the tools to collect that data and use it in a useful way."

StratoPro is available now starting at $350,000. Some customization is needed for each fab, Maniar said.

- Richard Goering
EE Times

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