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Choosing the best bumping option

Posted: 01 Jun 2006 ?? ?Print Version ?Bookmark and Share

Keywords:jean ramos? advanced interconnect technology? silicon? eda? design talk?

The flip-chip packaging market has rapidly grown in recent years, bolstered by market demands for increased package performance and smaller form factors, an increase in infrastructure, and finally, the development of new substrate technologies and assembly processes.

Because of flip-chip packaging's improved performance reliability, smaller footprint capabilities and compliance with lead-free initiatives, IC assembly and test services (SATS) provider Advanced Interconnect Technology Ltd (AIT) has signed a license agreement with Advanpack Solutions Ltd to begin using the technology on AIT's lead-frame-based packages, specifically quad flat no-lead (QFN) styles.

A few hurdles should be conquered, however, before flip chip could become a reality.

One is that the emission of alpha particles from lead using standard solder bumps can cause "soft" errors in embedded memory. To avoid damage from alpha particles, lead should be placed at a certain distance. Here, copper pillar bumping (cpb) has an advantage because of its copper standoff and lead-free solder tip.

Reliability boost
Additionally, the increased copper strength of CPB technology over traditional solder enables increased reliability and performance. The high standoff of the copper pillar bumps allows for easier flow of underfill between bumps, guarding against voiding.

A flip-chip package such as a QFN can take on a greater amount of I/Os because of the fine-pitch capability of the CPB technology. With an available pitch at 80m, the designer can add an even greater number of I/O pads both in a traditional perimeter array and in advanced, fully populated array QFN-style packages. Increased flexibility at the package design level can allow the overall package footprint to shrink, which is crucial for meeting the demands of next-generation applications.

For RF and power device applications, CPB has better electrical and thermal performance compared with standard solder bumps or wire-bonded packages. CPB has a 9x resistivity improvement and 8x thermal improvement over standard packages. Rds(on) for MOSFET devices can also improve to 40 percent.

Unique shapes for CPB are available for different device applications, such as bar-shaped structures for excellent thermal and electrical performance and rectangular ones for Faraday shielding. Other customized shapes depend on the application.

CPB is completely lead-free, using a pure tin solder tip. With Europe- and Asia-based initiatives taking effect, package technologiesincluding the bumping materialsshould meet these strict requirements.

It is important that chip designers meet with their SATS provider to see the bumping technologies offered and to determine if bumping technology provides the right performance and reliability for their individual design requirements.

Here are some key attributes designers should be aware of when considering migrating from a wire-bonded package to a flip-chip package using CPB:

  • CPB can apply to the typical pad layout used for wire bond by means of a redistribution approach, low-profile application or better thermal and electrical performance.

  • CPB can replace multiwire-bond connections with a single bump or finer pitch for high-standoff applications.

Options and flexibility remain key factors for bumping technologies. Careful consideration should be given to all the trade-offs, including environmental, material set, performance, industry infrastructure and price.

- Jean Ramos
Director of Technology Development, Advanced Interconnect Technology

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