Symposium to mull 45nm challenges

Technologists attending the 2006 Symposium on VLSI Technology in mid-June will hear about multiple facets of 45nm processes—ranging from strain techniques to high-k dielectrics and metal gates.

The symposium will focus on nonvolatile memory technology, drawing on a roughly equal number of companies from the West and the East. The sessions will run from June 13-15 in Honolulu, Hawaii, overlapping the 2006 Symposium on VLSI Circuits, scheduled for June 15-17 at the same venue.

A keynote speech on the technical challenges within the 45nm technology generation, which enters commercial production in 2008, will be given by Hans Stork, senior vice president of silicon technology at Texas Instruments Inc.

The symposium will offer multiple presentations on silicon oxide nitride oxide silicon (Sonos)-type flash from Samsung Electronics, including one that will describe a Sonos-type flash with 4 bits per cell stored in the nitride layers.

And Intel Corp. will describe a 32nm multigate transistor that combines fully-depleted technology, high-k dielectrics and strained silicon.

A team from Chartered Semiconductor, IBM, Infineon Technologies and Samsung Electronics will detail the strain techniques used for a low-cost process at the 45nm node. For the high-performance PFET transistors, the team was able to avoid using embedded silicon germanium junctions, which require an extra mask layer and which can impact yields. The IBM-led alliance relies instead on stress techniques based on nitride layers.

Another IBM paper will describe a more complex strain approach on SOI wafers for less cost-sensitive applications.

Developed at the East Fishkill, N.Y.-based process development alliance, the low-cost, low-power-consumption 45nm process delivers drain currents of 840μA per micron for the NMOS transistor and 490μA/micron for the PMOS transistor at 1.2V, with an off-state leakage current of 1nA per micron.

Meanwhile, engineers from Fujitsu Ltd will discuss two 45nm flavors: a high-performance transistor and a low-operation-power version. Fujitsu's high-performance PMOS transistor uses an S-shaped silicon germanium source-drain structure, with a compressive stress liner, to exert a strain on the channel.

Fujitsu did not use a high-k dielectric, but adopted a graded nitrogen profile that has a nitrogen concentration of 22 percent at the surface of the dielectric, decreasing to 1 percent at the interface with the substrate. With a 30nm gate length, the NMOS transistor has a drive current of 1,042μA/micron, while the PMOS transistor is rated at 602μA/micron.

Engineers from Freescale Semiconductor Inc., together with researchers from Soitec, the Crolles, France-based vendor of silicon-on-insulator wafers, will discuss a combination of local and global (substrate-level) strain engineering on SOI wafers. The paper abstract describes a strained silicon-on-insulator, or SSOI, process, which combines a very thin layer of active silicon on an SOI substrate. The approach uses dual nitride capping layers and embedded silicon germanium at the source and drain regions. The result: a 30 percent reduction in gate leakage with significant performance enhancements, the companies claim.

Another paper from Freescale, Soitec and STMicroelectronics combines SSOI technology with a high-k dielectric (hafnium dioxide) and a metal gate composed of titanium nitride. The team created prototype devices with a gate length of 25nm, and reported drive-current improvements of 16 percent, according to an abstract of the paper. Freescale worked closely with Soitec, which provided bonded SOI wafers with global strain. "The wafers have to be manufacturable and cost-effective. That takes a lot of collaboration," said Bich-Yen Nguyen, a silicon technology research manager at Freescale.

The VLSI circuits symposium, now in its 20th year, is moving beyond its early emphasis on memories to three general topics: wireless communications, ranging from WLANs to circuits for TV transmission to mobile devices; data converters; and serial interface circuits. And in all of those areas, low power consumption is becoming an overarching theme, said Wai Lee, a transceiver circuit designer at TI, who serves as the event's publicity chair.

- David Lammers
EE Times