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AMD processor roadmap closing gap with Intel

Posted: 07 Jun 2006 ?? ?Print Version ?Bookmark and Share

Keywords:HyperTransport? processor interface? interconnect? Turion? AMD?

Offering to license a crown jewel, Advanced Micro Devices Inc. (AMD) is opening its coherent HyperTransport processor interface to companies that want to build coprocessors for Opteron CPUs.

Access to the interface would allow other companies to design chip- or board-level products that can serve as closely coupled coprocessors to the host CPU, thereby improving system performance.

The announcement was just one of a dizzying array of disclosures AMD made at its semiannual technology day last week. The company shared aggressive technology and product plans, including a process road map intended to close the gap with Intel Corp.

Additional developments brought to light at the meeting include plans for a 65nm-based notebook processor and for a quad-core server processor that would open the door to multiprocessing systems with eight CPU chips, to deliver 32 program threads.

None of the announcements is likely to alter the competitive balance significantly between AMD and archrival Intel. But taken together, they reveal a company adamantly pursuing innovations and executing well on many fronts.

AMD's bid to license its coherent HyperTransport interface also demonstrates a growing confidence in its ability to expand the community of support for AMD's processor platforms.

"We are taking a very bold step by opening up our architecture. We know our competition will not do this," said Marty Seyer, senior vice president of the Commercial Business Segment at AMD.

The company detailed several new system platforms. A gaming-centric platform code-named 4X4 will extend AMD's commitment to deliver the highest-performance desktop systems, said Phil Hester, senior vice president and chief technology officer. Based on the dual-core 64bit AthlonFX processor and the Direct Connect architecture, the 4X4 can host one or two CPU sockets (up to four CPU cores) and support a pair of GPU-based graphics cards, such as the ATI Crossfire or Nvidia SLI, to deliver superior gaming performance, Hester said.

Three of the new platforms target the commercial segment. Torrenza will be the first Direct Connect computing platform to include the HTX coprocessor socket, which lets companies add customer-centric accelerators to improve multimedia, gaming, XML or floating-point applications, said Seyer. On motherboards with multiple CPU sockets, coprocessor chips can just drop into one of the CPU sockets. If a function becomes widely required, AMD could integrate it into the CPU or add it to the CPU package using multichip-packaging technology.

Focusing on security, virtualization and manageability, a platform code-named Trinity is said to provide better support for corporate IT managers. It will offer an open management partition to allow remote management of the platform as well as leverage the company's built-in Presidio (formerly Pacifica) security and virtualization technology, which breaks the tight coupling between hardware and software to allow a CPU to run multiple operating systems.

For low-cost client computing needs, a lightweight platform called Raiden, designed to deliver "just enough" computing for clients, promises to lower the overall cost of adding new clients to systems, Seyer said.

Unexpected move
The biggest surprise was AMD's decision to license coherent HyperTransport. The move could attract more silicon innovation around AMD-based computers and help the company prime a pipeline for future CPU features that would accelerate media, security, networking, XML, Java and more.

The noncoherent version of HyperTransport has long been an open, parallel chip-to-chip interconnect. But AMD has until today held tightly to its proprietary coherent version, which lets processors communicate directly, sharing cache data.

AMD will decide over the next 60 days whether it will make the technology available through the existing HyperTransport Consortium or through an adjunct group that would be created for the purpose. A set of APIs for HyperTransport coprocessors is also in development.

So far, only Cray and Newisys have licensed the technology for use with high-end interconnect chips in their own multiprocessing systems. But coprocessor vendors and OEMs that have expressed support for opening up the technology include IBM, Hewlett-Packard, Sun Microsystems and XML coprocessor startup Tarari.

AMD also disclosed work on a 65nm version of its dual-core Turion notebook CPU that is expected to debut in mid-2007. The company claims the device will require 40 to 60 percent less power than its current Turion CPUs when measured on an average range of applications. Enhancements come mainly in the form of a new memory controller and power-management technology geared for mobile systems.

High-end space
At the high end, AMD provided more details of a four-core processor for desktop and server systems. Slated for rollout in 2007, the CPU will sport four instead of three HyperTransport links, using version 3.0 of the technology and at least 2Mbytes of shared Level 3 cache (each core also packs 64Kbytes of L1 and 512Kbytes of L2 cache).

The cores will be enhanced to perform better branch prediction to reduce pipeline stalls, perform out-of-order load execution and perform 32byte instruction fetches. Instruction efficiency will also be improved, with up to four double-precision floating-point operations per cycle possible, along with dual 128bit loads per cycle. Internally, an enhanced crossbar will allow faster data movement within the chip. Dynamic independent core engagement will let the processor dynamically and individually adjust core frequencies for improved power efficiency.

The enhancements will let OEMs efficiently implement computers using eight chips without complex support logic, AMD said. Currently, optimal configurations for high-end AMD servers use four chips. The combination of more chips per system and more cores per chip pushes AMD deeper into high-end server territory, where it will compete with Intel's Itanium.

Chief executive Hector Ruiz said he wants AMD to capture 30 percent of the X86 server business. According to Gartner Group, the company currently has about 22 percent.

Overall, AMD says it still maintains a lead over Intel in performance per watt, though that lead may shrink as Intel begins to roll out its next-generation Core 2 Duo architecture over the next 12 months. Based on one AMD server comparison, the company could have as little as a 15 percent lead over Intel in system-level power consumption, much of it attributable to Intel's use of power-hungry, fully buffered DIMMs.

"We have the best X86 execution engine today, and we will have the best one next year," said Dirk Meyer, AMD's chief operating officer. "We have a lot of great engineers and they haven't been sleeping."

- Dave Bursky and Rick Merritt
EE Times




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