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Matsushita process enables air-gap interconnects for ICs

Posted: 08 Jun 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Mark LaPedus? Matsushita Electric? low-k? manufacturing process? IC design?

Matsushita Electric Industrial Co. Ltd described early this week what the company claims to be a viable replacement for conventional low-k films. The company has devised a new manufacturing process that claims to enable "air-gap" interconnect structures in advanced IC designs.

Matsushita's technology, dubbed Air Gap Exclusion (AGE), claims to enable copper interconnects with air-gap structures at "k values" of 2.5 and below.

"The AGE process would realize a new age interconnect scheme," according to a paper from Matsushita at the International Interconnect Technology Conference (IITC). The company did not comment on when it would put the technology in production.

For some time, leading-edge chip makers have been struggling to integrate copper interconnects with new and complex low-k dielectric films as a means to boost the performance in chip designs.

While many chip makers were able to deploy low-k films at the 130nm and 90nm nodes, there is talk that the interconnect technology will hit the wall. For years, air-gap techniques have been proposed as the replacement for low-k films, but there is an assortment of problems associated with this technology in production: damage to lines; misalignment of vias and contacts; and degradation of the planarity at large spaces, according to the Japanese company.

By using AGE, Matsushita claims that it has resolved many of those issues. The company said that it has devised air-gap interconnects with "low damage" to the copper lines at "sufficient electrical characteristics and reliability."

In the paper, the company outlined a process sequence for this technology: "At first, [copper] lines are fabricated in a FSG film. A TaN film and a Ta film are used as a barrier layer and a glue layer, respectively. Next, a cap layer is selectively deposited on the copper lines.

"Then, a SiN film is deposited over the FSG film and the cap layer, and a resist pattern is formed on the SiN film. The resist pattern is used to exclude air gaps, according to the paper. "After forming the pattern, the SiN film and the FSG film are removed by dry etching and wet etching, respectively."

- Mark LaPedus
EE Times

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