Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Interface
?
?
Interface??

PCIe gets a version 2.0

Posted: 13 Jun 2006 ?? ?Print Version ?Bookmark and Share

Keywords:PCI Express? PCI-SIG? Ramin Neshati? I/O virtualization? interconnect?

The 2.5Gbps PCI Express interconnect is slowly shifting gears into a 2.0 version expected by the end of the year to double data rates.

The latest details on the schedule as well as work on a handful of new features and form factors!and a sneak peak ahead at the future!was the focus of the PCI-SIG annual meeting in San Jose, California last week (June 8-9).

Originally, the version 2.0 was set slated for release in late 2005. Now the group plans to conduct some in-depth tests based on the current 0.7 draft to arrive at a final version before the end of 2006.

Generally doubling speed in a given design means halving distance. Thus engineers have several open questions whether some connectors, board materials or other aspects of existing designs may have to change to accommodate the new speeds in the existing form factors.

"One of the big concerns is can version 2.0 handle all the Express form factors. There's a whole new round of simulations going on to check that right now," said Michael Krause, an interconnect expert in Hewlett-Packard's x86 server group. The simulations may take two months, he added.

What's clear is "all the design budgets for 2.0 will be very tight," said Ramin Neshati, a technical program manager from Intel Corp. who has worked on version 2.0 from its inception.

The 400ps jitter margin of the 2.5Gbps version 1.1 will shrink to 200ps for version 2.0. Clocks and PLLs will have to handle most of the narrowing restrictions, Neshati added.

One recent proposal suggests limiting Express 2.0 implementations to 85-ohms impedance on a PC board. However, simulation tests may show the existing 100-ohms levels are adequate, at least in some implementations.

Meanwhile, designers have identified a handful of new features they will add to the 5Gbps version. They include an access control feature to give software an ability to control packet routing on the interconnect and prevent hackers from spoofing and rerouting data, primarily for peer-to-peer traffic. The feature will be implemented for Express chipsets, switches and multifunction devices.

Another new feature will notify software in cases when a link automatically shifts to a lower speed or width. An update to the link-training state machine for Express will let software also control the configuration and adjust speed of Express 2.0 links.

Graphics chips need the new 5Gbps speeds to drive higher performance as well as open the door to using the fast channels to eliminate graphics memory in favor of using the systems main memory!even when graphics are on a card off the motherboard. However, desktop and notebook computers may implement a mix of 5Gbit Express for graphics and 2.5Gbit Express for everything else for a few product generations.

In servers, both serial ATA and serial-attached SCSI standards are preparing a move up from 3Gbps to 6Gbps speeds that will want Express 2.0. In addition, multiport controllers for Ethernet, Infiniband and Fiber Channel will want the faster system link.

Cables and cards
The PCI-SIG also provided an update on work on a variety of form factors for Express add-on products. Work on an Express card designed to plug into the display side of notebook computers has been suspended because engineers found they could not produce such cards at low enough costs given problems in heat, thickness of the cards and electromagnetic shielding from LCD modules.

Instead, the group will define a half-size mini-card for internal use in the base of notebooks and small desktops. The cards will be about 30mm wide and 26mm tall and designed so that two of them can fit into the same area as an existing full sized mini-card. They will be mainly used for enabling last minute build-to-order notebook configurations for Bluetooth, Wi-Fi and other wireless standards.

Separately, work on a cabled version of PCI Express is slowly moving forward. A 0.7 draft of the spec!that now includes 16x as well as 1x, 4x and 8x versions!went out to SIG members last week. Cost of the cables is still unclear.

The cables would be used to link servers in different racks, act as a fast docking connection or link separate compute and storage "bricks" in disaggregated desktop designs. It will not be clear whether the cables, rated for distances of up to 10m at 2.5Gbps, will be able to work with the 5Gbps version of Express until the basic Express 2.0 simulation work is completed.

Work continues in the SIG on I/O virtualization that will serve both the existing 1.1 and next-generation 2.0 versions of Express. The spec could be finished as early as the end of 2006. It includes separate specifications for device sharing, address translation services (ATS) and both single- and multi-processor systems.

The ATS feature will require a relatively small number of new hardware gates on both I/O end points and controlling processor chipsets to implement what is essentially a caching function.

Fast forward
Finally, SIG leaders provided a brief peak ahead at their thinking on the more distant future. The group hopes to deliver another generation of Express on copper traces that could deliver a speed boost of 1.5 to 2.2 times the 5Gbps rate before a transition to optical links. The SIG is conducting lab work on receiver equalization and transmit pre-emphasis to find out what techniques could bring 10Gbps speeds to PC price points in any reasonable time frame.

"Everyone wants to go to smaller, narrower, faster and less power hungry links. Keeping the power the same is a tough challenge," said Neshati. "We don't have a schedule or a name for this new generation, but it should emerge when the market is ready," he added.

Some graphics companies have suggested that with 10Gbps links, discrete graphics products could essentially eliminate any advantage of today's CPU chipsets with integrated graphics that are popular in mainstream PCs. Such products are likely to become drivers for the third-generation Express work, one engineer said.

- Rick Merritt
EE Times




Article Comments - PCIe gets a version 2.0
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top