Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Real-life power gates a bigger challenge

Posted: 16 Jun 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Anand Iyer? George Kuo? cadence? spotlight? power?

The architectural concept of shutting down a region or sub-block of an IC to reduce power requirement seems logical and straightforward to logic designers. However, implementing power gating in real designs can be extremely challenging.

Powering down and ramping up require transition cycles and need simulations to understand power savings during power down vs. switching power used during ramp up. This must also be balanced against the area needed to implement the technique and any performance degradation resulting from switch-off.

Power can be shut down externally or internally. External shutdown supplies voltage-control functions to deliver variations of power supplies at the system/board level. In doing this, reliable isolated power must be provided to various subsystems of the chip and may limit the number of separate power supplies.

Power gating is implemented either by a fine-grain approach building sleep transistors in every standard cell or a coarse-grain approach aggregating sleep transistors at the logic-block level. Designing the power-gating control signal requires analyzing buffering/drive-strength to consider reliability issues such as electromigration and IR-drop timing performance. Output signals from a block being switched off must be isolated because they are in a metastable state during switch-off.

Before shutdown, consider the minimum states of the logic block to be preserved for faster "wake-up" cycles. Preserving the logic state involves saving critical information into a memory function to be maintained during power-down. Power-on-reset, scanning the state from a RAM or saving the state into local "state-retention" registers can all restore a block's logic state after shutdown. Although using state-retention registers incurs penalties on area and routability, it offers faster ramp-up and usually requires less control logic to save and restart the current execution state than software restart or in-memory storage.

Power gating implementation starts with synthesis that understands the power domains, and can insert isolation cells and state-retention registers as needed. In turn, the physical implementation must understand the special power connection needs of the header/footer switches. Physical implementation also should insert the switches to complete the place and route of the power domain blocks and optimize switch size.

A correct design requires timing and signal integrity analyses to account for additional IR drop in switches, delays through isolation cells and sensitivity of control signals to noise. Large SoCs require formal techniques to verify the correctness of the gate-level netlist and low-power functions. Equivalency checking should include power domain recognition, isolation/power switch-enables verification and state retention's sleep/wake sequence checking.

Power gating requires a system-level understanding of where to add power gates, and how and when to control them. A domain-aware infrastructure can help reduce overall turnaround time.

- Anand Iyer, George Kuo
Cadence Design Systems Inc.

Article Comments - Real-life power gates a bigger chall...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top