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Just how low can FPGAs go?

Posted: 16 Jun 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Richard Goering? EE Times? spotlight? power? silicon?

Perhaps the biggest barrier to field-programmable gate array (FPGA) use in applications is their high power consumption. But low-power FPGAs are technically feasible and may become economically viable as future nodes shrink.

Power techniques
At FPGA 2006, researchers from Xilinx Inc. showed the symposium that a low-power FPGA can be built by using well-understood design techniques, like voltage scaling, power gating, low-leakage configuration memory, and partial and full-sleep modes. The resulting Pika architecture, said to be suitable for battery-powered consumer applications, claims to consume 46 percent less active power and 99 percent less standby power than the baseline Spartan 3 architecture.

Whether the architecture is commercially viable is another question, given its 40 percent area penalty. Since area translates into cost, it is a key concern for handheld consumer applications. But remember that FPGA vendors are leading the charge to lower process nodes. Moreover, FPGAs will have far more capacity at 65nm, 45nm and beyond.

For many applications, the real advantage of these lower process nodes won't necessarily be larger gate capacities. It will be the ability to "waste" gates to maximize power or performance. A 40 percent area penalty may not be such a big deal at 65 or 45nm, but a 46 percent power savings probably is.

Furthermore, FPGA vendors are now starting to use low-power design techniques. Altera, for example, recently introduced a technique for power-aware mapping of embedded random-access memory blocks. Below 90nm, FPGA vendors realize that they are in an era of "power-constrained scaling," said Vaughn Betz, director of engineering at Altera. That will result in new FPGAs, he said, with twice the capacity and no more power consumption than devices of previous generations.

Some researchers argue that as we head into the nanotechnology realm at 32nm and below, we'll need to move to FPGA-like fabrics anyway. Jan Rabaey, professor at the University of California at Berkeley, said that the ideal "nanoscale silicon implementation platform" will be programmable, regular and redundant. Such fabrics better tolerate errors and variations and are easier to manufacture. Rabaey also noted that they offer many opportunities to minimize power consumption.

Yes, regular fabrics take up more transistors, but in the nano-realm, we'll have lots of transistors to spare. What we won't have is a lot of time to design something that works and meets time-to-market requirements.

Make no mistake. At any given process node, FPGAs will never catch up with ASICs or custom integrated circuits when it comes to performance, power minimization or volume cost. But as we head to 65nm and below, FPGAs may be a "good enough" solution for a widening range of applications. Dive deeper into 45nm, 32nm and beyond, and you may see more and more devices that look like FPGAs.

- Richard Goering
EE Times

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