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NEC, NEC Electronics introduce high-k CMOS tech

Posted: 26 Jun 2006 ?? ?Print Version ?Bookmark and Share

Keywords:55nm? immersion lithography? LSI? large-scale integration? NEC?

NEC Electronics and NEC introduced a new device technology that is said to deliver both low standby power consumption and high operating speeds for system LSIs using design rules for 55nm and below.

To implement 55nm node design rules, the companies used an immersion lithography process that allowed the pitch of the M1 interconnect layer to be reduced to 160nm and enabled an SRAM cell size of 0.432m2. Compared to the 90nm processes, transistor density is said to be 2.5 times higher.

Features of the new technology being touted include: a high-k dielectric for transistor threshold control; use of process-induced stress techniques for electron and hole mobility; and the use of argon fluoride immersion lithography, which enabled the development of ultra-small SRAM cells.

By optimizing shallow trench isolation stress, sidewall stress and silicon nitride stress on the gate, it was possible to improve the performance of both NMOS and PMOS. According to the companies, these techniques allowed drive currents to be increased by 22 percent for NMOS and 31 percent for PMOS, compared to 65nm nodes from NEC Electronics.

NEC Electronics will use this technology to implement low-power/high-performance system LSIs for applications such as mobile devices and networking.

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