Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Synopsys rolls out 2006.06 version of IC Compiler

Posted: 29 Jun 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Dylan McGarth? Synopsis? IC Compiler? 2006.06?

Top tier EDA vendor Synopsys Inc. recently rolled out the last version of its next-generation place-and-route tool, IC Compiler.

According to Synopsys, the tool's 2006.06 release offers advances in the areas of integrated design planning, enhanced physical test, advanced low-power design, true concurrent multicorner/multimode optimization and design-for-yield techniques.

Some industry analysts and observers have questioned the interest level in IC Compiler, which was introduced in March 2005, suggesting that the company's more mature Astro physical implementation tool provides enough functionality for the majority of the company's customers. But Synopsys Monday said IC Compiler has drawn customers from a broad class of applications, including designers creating 65nm designs as well as mature 180- and 130nm products. Several customers are scheduled to detail their tapeout experiences using IC Compiler at the Design Automation Conference here next month, Synopsys said.

"IC Compiler has seen strong support among our key customers who have a diverse family of designs and are often at the leading edge in adopting new technology," said Antun Domic, senior vice president and general manager of Synopsys' implementation group, in a statement.

Synopsys said the 2006.06 release allows flat floorplan creation and refinement in the same environment as physical implementationplacement, clock tree and routing. These capabilities utilize technologies from the JupiterXT tool for floorplanning, automatic high-quality macro placement, and automatic power-network synthesis and analysis, the company said.

The 2006.06 release also includes enhanced capabilities for low-power design, manufacturing testability and design-for-yield, Synopsys said. It provides improvements in multi-Vt leakage power optimizations as well as advanced leakage management with MTCMOS power-gating, according to the company. The release introduces a new syntax for capturing power-domain specifications and enhances Synopsys' Liberty library format for MTCMOS power modeling, according to the company.

In the area of DFM, the 2006.06 release adds to the existing set of capabilities for impacting yield during design, including intelligent multipattern via optimization, timing-driven wire spreading, timing-driven metal fill and critical area analysis, Synopsys said. New capabilities include timing-driven via redundancy, staggered metal fill and timing-driven half-pitch wire spreading after detail route, according to the company. Another new capability in limited customer availability is lithography "hot-spot" fixing, Synopsys said.

The IC Compiler 2006.06 release is available immediately, Synopsys said. Pricing information was not made available.

- Dylan McGrath
EE Times

Article Comments - Synopsys rolls out 2006.06 version o...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top