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Avago unveils 65nm SerDes core

Posted: 29 Jun 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Avago? serialization/deserialization? SerDes? IP core?

Avago Technologies Inc., the semiconductor spin-off of Agilent Technologies Inc., recently claimed that it is among the first manufacturers to validate its serialization/deserialization (SerDes) core in 65nm CMOS process technology.

Manufactured on a foundry basis by Taiwan Semiconductor Mfg Co. Ltd (TSMC), Avago's embedded SerDes IP core is said to offer low jitter capabilities, making it possible to integrate as many SerDes channels as needed.

Each core operates at up to 12.5Gbps, according to Avago. The new SerDes core features a clockless decision feedback equalization, on-chip BERT for channel bit error rate optimization, an LC-based oscillator for improved power-supply noise rejection, and 1149.6 AC-Extest for testing AC-coupled connections.

"This technology advancement, representing our fifth generation SerDes core, will continue to provide networking and computing OEMs with competitive advantages," said James Stewart, vice president and general manager of Avago Technologies' Enterprise ASIC division, in a statement.

Seeking to reposition itself as a pure-play measurement company, Agilent last year sold its troubled semiconductor business to equity fund companies Kohlberg Kravis Roberts & Co. (KKR) and Silver Lake Partners for $2.66 billion. In addition to selling its Semiconductor Products Group, the company last year also confirmed it would spin off its SoC and memory test businesses in 2006.

Rechristened Avago, Agilent's former semiconductor products group became a standalone company late last year.

- Mark LaPedus
EE Times

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