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Micronas tapes-out HDTV chip with Synopsys solution

Posted: 29 Jun 2006 ?? ?Print Version ?Bookmark and Share

Keywords:tape-out? HDTV chip? Synopsys? EDA? Micronas?

Synopsys Inc. announced that Micronas has taped-out one of its HDTV chips using Synopsys' IC Compiler physical implementation solution.

Using the Galaxy design platform with IC Compiler optimization technology, Micronas was able to tape out this design at the required performance while achieving utilization in excess of 90 percent, revealed Synopsys in a press release.

The IC Compiler's Extended Physical Synthesis is said to be the architecture that increases the solution's efficiency by combining synthesis, placement, clock and routing in a unified optimization environment.

Another element used by Micronas to reduce the die size was IC Compiler's congestion-reduction algorithm that aims to fix local congestion hot-spots and increase the maximum achievable utilization. The design-for-test MAX tool was used to implement test compression that can reduce testing costs by up to 50X. This design is said to have benefited from IC Compiler's physical test optimization techniques, including scan chain repartitioning and reordering for reduced congestion.

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