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Synopsys expands test portfolio with NanoTime

Posted: 30 Jun 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Synopsys? NanoTime? static timing analysis?

Synopsys Inc. has announced the availability of NanoTime, a next-generation transistor-level static timing analysis solution that promises concurrent timing and signal integrity (SI) analysis to address emerging custom circuit design challenges. NanoTime is a new addition to the company's circuit simulation and analysis product portfolio that includes NanoSim, HSIM and HSPICE tools for circuit simulation, and ESP-CV for symbolic simulation.

According to the company, the new device also delivers significant performance and capacity boost to analyze complex transistor circuits overnight with HSPICE accuracy. Its seamless integration with PrimeTime static timing analysis solution enables chip-level analysis of designs that includes both gate- and transistor-level blocks.

"We have been successfully using Synopsys' PathMill transistor level static timing analysis solution over the past decade for silicon-accurate analysis on a variety of ARM processors, including ARM7, ARM9 and ARM10 processor families," said Keith Clarke, VP of technical marketing, ARM. "Now, with NanoTime, we believe we can achieve higher predictability and greater productivity over PathMill. NanoTime not only recognizes our custom design structures, but also offers HSPICE correlation. We are currently incorporating NanoTime in our 90nm design flow."

Synopsys said NanoTime offers higher predictability and improved productivity to custom designers over existing solutions. Its concurrent timing and SI features enable designers to accurately and quickly identify timing issues early and avoid expensive silicon re-spins. With an ability to recognize complex custom design structures and its embedded NanoSim technology for dynamic circuit evaluation, the company said the device helps ensure silicon-accurate analysis. NanoTime promises the performance and capacity required to perform overnight analysis of complex circuits with over one million transistors. Designers' productivity is further boosted by significant ease-of-use features, including interactive static timing analysis, extracted timing model (ETM) creation, and seamless integration with PrimeTime chip-level analysis tool, the company explained.

"Synopsys' comprehensive circuit simulation and analysis product family has been deployed in the most demanding microprocessor, DSP and memory designs for the last decade," said Antun Domic, senior VP and general manager, Synopsys Implementation Group. "Our customers are seeking solutions that offer higher productivity and better predictability in their custom design flows. With the introduction of NanoTime, we deliver a comprehensive transistor-level analysis solution that addresses our customers' most demanding requirements."

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