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Comms DSP engine packs four StarCores

Posted: 01 Jul 2006 ?? ?Print Version ?Bookmark and Share

Keywords:David Lammers? EE Times? Freescale Semiconductor Inc.? DSP engine? StarCore SC3400?

Freescale Semiconductor Inc. has developed a DSP engine based on four StarCore SC3400 cores aimed at communications infrastructure equipment and Internet Protocol (IP) multimedia subsystem gateways.

The MSC8144 will begin sampling in Q3 2006, with volume production starting early next year. The DSP chip is based on a 90nm silicon-on-insulator technology, which delivers performance of up to 1GHz for each of the four cores. The signal-processing device is placed side-by-side in a single package with a 10.5Mbyte DRAM and 128bit, 400MHz interface between the logic and L3 memory chips.

The MSC8144 is a successor to the MSC8122, which arrived on the market in early 2005, said Altaf Hussein, senior product marketing manager at Freescale's network computing system group. He claimed that with a peak performance of 16,000 MMAC operations per second, the 8144 is the highest-performance DSP yet announced.

Telecom carriers are increasingly dealing with media-rich content, such as H.264 and MPEG-4 video decoding. Video transcodingconverting from one format to another standard's format to accommodate the small screen sizes and different resolutions in portable phones and media playersalso demands increasing signal-processing performance. Freescale has partnered with Trinity Convergence on video transcoding technology, Hussein said.

The quad core will also be used in enterprise VoIP gateways and videoconferencing systems, wireless base stations and a systems category now called IP multimedia subsystem (IMS) gateways.

"A prime example of network convergence is 'access anywhere' communications enabled by IMS gateways," said Lynelle McKay, general manager of Freescale's digital systems division. As users change locations, they demand QoS for video, voice and data services. The 8144 provides "the performance to deliver these converged-network capabilities within a low-power envelope," McKay said.

While software from previous StarCore-based products can be used on the quad-core engine, Freescale engineers have developed more efficient, specialized instructions for Viterbi and video algorithms. The company claims they double performance, resulting in a product that can handle three times as many (13 instead of four) H.264 video channels at 30fps of CIF-resolution video, and roughly double the number of VoIP (G.729AB) channels (336 vs. 168) compared with the dual-core MSC8122 device.

Hussein said Freescale has taken processing blocks from the company's MSC8360 PowerQuicc product and brought them to the MSC8144, including a QuiccEngine for ATM, IP processing and software reuse. "That allows us to offload functions from the DSP coresvery few DSPs have IP processing elements on the same die," he said. "We looked at the bottlenecks out there and came up with what we believe is a balanced processor."

Using a programmable QuiccEngine helps on QoS delivery. And the 8144 has a non-blocking switch fabric, "which means there are no blocking elements on this chip," Hussein said.

Asked about power consumption, marketing communications manager Kim Mallinger said "the design team came back with an estimate of 4.5W at 800MHz for all four cores running EFR channels to the maximum, with packet and TDM peripherals active."

By using a DRAM in the same package, there is no need to attach external memory to each device, saving an additional 1W over competing solutions, she added.

The product will be sold in 1GHz and 800MHz versions in a 783-pin, 29-by-29mm flip-chip PBGA package. Pricing starts at $180 in 10,000-unit quantities.

- David Lammers
EE Times




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