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Tool suite handles design complexity

Posted: 01 Jul 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Richard Goering? EE Times? FPGA tools? Altera Corp.? Quartus 6.0 tool suite?

As design complexity increases, FPGA tools and design flows are looking more and more like ASIC design. Altera Corp. accelerated that trend recently with its Quartus 6.0 tool suite, which includes a timing analyzer that's said to pave the way for next-generation 65nm FPGAs.

The star attraction in Quartus 6.0 is TimeQuest, a static timing analyzer based on the industry-standard Synopsys Design Constraint (SDC) format. It promises more flexibility for challenges like clock-multiplexed designs and source-synchronous interfaces, as well as a future capability to handle such issues as on-chip variation.

Quartus 6.0 is also known to ease team-based design with a project manager interface feature. Other improvements in the release include SystemVerilog support, an enhanced I/O pin planner, and HSpice models of Stratix II single-ended outputs for signal integrity modeling of PCBs.

Quartus 6.0 doesn't accompany any new device announcements, but TimeQuest will help support the next generation of FPGAs, said Chris Balough, director of software and Nios marketing at Altera. "TimeQuest and our adoption of native SDC position us for complex high-density FPGA design and ready us for the rollout of 65nm devices coming soon," he said.

FPGA designers were able to get by with fairly simple timing models for many years, Balough said, but today, they are reaching a point where device density, performance and complexity require something more. In particular, he said, challenges like source-synchronous and clock-multiplexed designs are revealing the shortcomings of existing timing constraint formats.

But Balough emphasized that Altera is not abandoning its existing Classic static timing analyzer, which he said continues to be appropriate for the bulk of FPGAs being shipped today. TimeQuest, he said, is an optional capability for users who have an SDC background or who face high-density, complex devices that are running into limitations with existing tools.

One clear benefit of SDC is that most ASIC designers use it, making it a natural choice for ASIC designers who are turning to FPGAs. But SDC also provides a more "precise" language with which to define timing relationships, Balough said. For example, with the 6.0 release, Quartus will model rise and fall times for the HardCopy-structured ASIC family.

Altera has not yet decided to what extent rise and fall time modeling will be made available for FPGAs, but SDC at least provides the capability, Balough said. Similarly, SDC allows the modeling of on-chip variations, but Altera has yet to provide that capability to its users.

What is available in the Quartus 6.0 release, however, is an easier way to model source-synchronous FPGA-to-DDR interfaces. Such modeling requires one signal to be controlled in relationship to another. Without SDC, that's an iterative process; but with SDC, the timing analyzer automatically manages the relationship, Balough said.

Multiplexed clocks are also better supported in Quartus 6.0. With the Classic timing analyzer, noted Alessandro Fasan, senior manager of software technology marketing, users have to write constraints for each mode of operation. With SDC, he said, users write constraints just once and tell the timing analyzer which path to analyze given the clock frequency.

Balough noted that TimeQuest provides a standalone cockpit for all timing reporting, while the Classic tool's reporting is more distributed through other user functions. TimeQuest thus provides more flexible control over how timing is reported, he said. A new feature is the ability to generate SDC constraints from the GUI itself using parameters entered by the user.

TimeQuest supports only Altera devices, and it doesn't have all the capabilities of Synopsys' PrimeTimethe most widely used ASIC timing analyzer. But Altera gives users the option to use PrimeTime, Balough said. "With the 6.0 release, the PrimeTime interface requires a little manual intervention from the user, but that will disappear with the next release," he said.

The expanded team-based design features in Quartus 6.0 are an extension of the incremental compilation feature introduced with previous releases. Incremental compilation lets users divide designs into physical and logical partitions for synthesis, placement and routing. Until now, however, that partitioning required a "fairly detailed manual process," Balough said.

The team-based design feature in Quartus 6.0 includes a project manager interface for managing device resource and timing budgets. The interface makes it easier to subdivide the project in a way that will eliminate resource conflicts when design blocks are combined at the top level. It's particularly valuable for geographically-dispersed teams, Balough said.

Also new in Quartus 6.0 is support for SystemVerilog. At present, said Fasan, Altera supports design implementation constructs in the IEEE 1800-2005 SystemVerilog standard, and it is examining which verification features to support in future releases.

The I/O pin planner capability in Quartus helps users make sure they get a legal pinout, but previous releases required a complete netlist. In the new version, users only need to identify the intellectual property they want to use, according to Balough.

Altera is also releasing HSPICE models for the first time. These are for PCB and signal integrity engineers who want to ensure the FPGA will work after it's placed on the board. The current offering, however, is limited to single-ended outputs for Stratix II devices. "This is really just a first step," said Balough.

Other new features in Quartus 6.0 are aimed at the SignalTap II debugger. Those features include a power-up automatic trigger feature, an improved Matlab interface and a Nios II CPU SignalTap disassembly plug-in.

Quartus 6.0 software is currently available, with an annual subscription of $2,000 for a node-locked PC license.

- Richard Goering
EE Times

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