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DFM tool targets parametric yield

Posted: 01 Jul 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Richard Goering? EE Times? design-for-manufacturability? Blaze DFM Inc.? Blaze MO?

Claiming to open a new chapter in IC design-for-manufacturability (DFM), startup Blaze DFM Inc. recently rolled out Blaze MO, said to be the first "electrical" DFM solution. The company maintains that its offering improves leakage and timing by optimizing and annotating design data for the optical proximity correction (OPC) process.

Blaze DFM is one of many startups in its area, but the company believes its electrical DFM approach is unique. This method, the company says, turns design requirements into manufacturing directives, and improves parametric yield through better control over leakage, timing and variability. In contrast, tools with a "geometric" focus are more concerned about issues like wire spreading, lithography simulation and critical-area analysis.

"We're directly operating on the things designers care abouttheir timing and power requirements," said Dave Reed, Blaze DFM's VP of marketing and business development. "Other approaches are dealing with shape fidelity, and trying to make sure all the shapes are somehow fabricated to what the designer has drawn."

Reed said that Blaze MO is performing optimization instead of just putting out reports. Rather than spreading wires or doubling vias, the tool manipulates gate lengths to reduce variability and achieve the best trade-offs in terms of leakage and performance. Blaze MO claims to require no significant changes to existing flows or signoff methodologies.

Customer announced
Blaze DFM was founded in 2004. Noted CAD researcher Andrew Kahng, who is taking a leave of absence from his position as professor of computer science and engineering at the University of California at San Diego, is co-founder, chairman and CTO. Blaze DFM announced last May that Jacob Jacobsson, former CEO of Forte Design Systems, is now Blaze DFM's chief executive. The company has raised $8 million and has 20 employees.

Blaze MO is currently ready to ship, Reed said, and one announced customer is STMicroelectronics. The tool has support from five foundries, he said, but can currently name only Chartered, IBM and Samsung. The intended target is design teams, and Blaze is selling to both IDMs and fabless IC companies.

Reed said users can expect a 40 percent reduction in leakage and a 60 percent reduction in variability at the 65nm process node. The product accomplishes this by causing gate lengths to slightly lengthen in places where performance is not critical. Conversely, it can shrink gate lengths where performance is critical, allowing an improvement in timing of up to 10 percent.

The optimization runs at a full-chip level, Reed said. If the placement and routing is flat, Blaze MO runs flat; if placement and routing is hierarchical, Blaze MO follows suit. One chip tackled by the tool, Reed said, had 500,000 instances at the top level and nine other macro blocks.

"It runs automatically, but designers who want to provide guidance and run different experiments will get better results than somebody who just runs it one time," Reed noted.

To run Blaze MO, users need to provide an LEF-format layout file and generate an OpenAccess database. The next step is to input Liberty cell libraries, a Verilog netlist, timing constraints and parasitic information. Blaze MO produces a modified Verilog netlist that can be checked with a signoff timing tool, like Synopsys' PrimeTime.

"What we're doing is changing the performance of the individual transistors, which has the potential to change the timing," Reed said.

Thus, he said, the Verilog file is checked by a signoff timing analyzer to make sure the timing hasn't changed.

In the final step, Blaze MO takes in GDSII files and produces an annotated GDSII file that's passed to an OPC tool.

"We don't touch the designers' layers, but we put in a new layer for the foundry, specifically for the Blaze annotations," Reed said. "We're not changing what the designer thinks of as design, but we are changing how the design is represented in silicon."

All that's needed, Reed said, is a slight change in gate lengthjust a few nanometersto make a significant difference in leakage and variation. Blaze MO is said to work within any IC placement-and-routing flow and with any commercial OPC tool.

Validation process
Cooperation with foundries is essential for the success of Blaze MO, Reed said. "Foundries have to take this annotation layer and use it to modify their OPC results," he said. "We had to go through a big validation process, including producing silicon, to find the acceptable range of biasing and to agree on how it will be communicated."

The validation process included Spice-level testing on a range of 90nm and 60nm process technologies, lithography simulation studies and detailed silicon studies using proprietary test chips and IP cores. Fabricated silicon was used to compare Blaze-optimized and production versions of a design by writing both versions on the same reticle.

Blaze MO is available today starting at $275,000 annually.

"We're not about single licenses; we're about doing enablement for the whole site," said Jacobsson.

- Richard Goering
EE Times

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