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ARM 32bitters give designers a choice

Posted: 01 Jul 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Dave Bursky? ARM9E-based solution? STMicroelectronics? ST? STR910F?

A pair of 32bit ARM-based embedded processors will let designers wrestle with a tough choicetake advantage of an off-the-shelf ARM9E-based solution from STMicroelectronics (ST) or design their own high-performance solution with the latest Cortex-R4 ARM core from ARM Ltd.

The STR910F family from ST combines Ethernet connectivity, an ARM9E processor core and large embedded SRAM and flash memories along with a large assortment of I/O support functions.

The ARM966E-STM core used in the STR910F series delivers better performance than previous ARM7-based solutions, said Mark Rootz, marketing manager for ARM9-based products in the Microcontroller Division at ST, because it accesses its instruction and data memories using two separate internal buses, thus enabling simultaneous access of both code and data.

"Each of these memories is attached to the core through a highly-optimized tightly coupled memory (TCM) interface for rapid access. The STR910F exploits this architecture by placing a high-speed burst flash memory on the instruction TCM, and a zero-latency SRAM on the data TCM," said Rootz. "The result is 96MIPS peak code execution at 96MHz (the highest peak performance for general-purpose flash ARM-based MCUs), and extremely efficient data movement between the CPU core and SRAM." In contrast, the ARM7TDMI CPU core shares a single bus for access to its instruction and data memories, making simultaneous access impossible. Both the ARM7TDMI and ARM966E-S cores execute the standard ARM and Thumb instruction sets.

The STR910F was given large memories to support the RTOS and TCP/IP stacks, in addition to complex control applications, said Rootz. SRAM sizes range up to 96Kbytes, the largest SRAM of all general-purpose ARM-based flash MCUs in the market today. Such large SRAM blocks are suitable for larger packet buffers, enabling faster serial communications. The SRAM can be protected by a battery or supercapacitor connected to the battery input pin; alternatively, the SRAM contents can be automatically destroyed for secure applications in response to a signal on the STR910F's tamper-detection input pin.

Flash memory sizes range up to 544Kbytes, configured into dual banks of read-while-write memory to support robust in-application programming for remote firmware updates, and also for EEPROM emulation. Each SRAM and flash memory can be used for instructions or data.

More MIPS
For much higher performance, ARM's Cortex-R4 processor core leverages an advanced microarchitecture with dual-instruction issue to deliver more than 600 Dhrystone MIPS when implemented in a performance-optimized 90nm process flow (based on the ARM Artisan Advantage library).The core runs the enhanced Thumb-2 instruction set and can trim cost and power consumption for system developers, said John Cornish, VP of marketing of the processor division at ARM. "The core occupies less than 1mm2 and consumes less than 0.27mW/MHz when fabricated in an area-optimized 90nm process flow," said Cornish. "This latest member of the Cortex processor family gives chip designers a high-performance processor for use in 3G phones, hard-disk drives, imaging and automotive systems, to name a few applications."

To get the higher performance, the Cortex-R4 uses an eight-stage pipeline vs. the five-stage pipeline in the ARM9E. In addition, the latter stages of the pipeline in the R4 were split into four parallel pipelines. Each parallel portion of the pipeline handles different instruction types so more can be done in parallel.

Designers can either get much higher throughput by optimizing the R4 for performance, or can achieve much lower perating power by delivering the same MIPS throughput as the 9E, but running at a lower clock speed to save power.

Improvements over the ARM9E core include the addition of branch prediction to avoid flushing the pipeline once the branch is executed. A direct-memory-access port was also added to the R4 core to improve data transfers over an enhanced version of the TCM interface.

To further reduce cycles, the R4 uses a 64bit Amba 3 AXI memory interface bus. The AXI bus lets the processor issue multiple outstanding addresses and supports data to be returned out of order.

The ARM Cortex-R4 processor is available for licensing, along with the Instruction Set Simulator and RealView Development Suite tools environment.

The STR910F line includes six devices, all in 80- or 128-lead lead-free packages. SRAM ranges from 64Kbytes to 96Kbytes and flash memory from 288Kbytes to 544Kbytes. The core runs at 1.8V 10 percent, and the I/O ring at 2.7V to 3.6V, over a temperature range of -40C to 85C. Comprehensive support from ST and third parties includes starter kits for $199. These kits include a compiler and debugger (limited code size), a JTAG debugging and programming cable, code examples and all hardware needed to begin a design. In lots of 10,000, per-piece prices for the STR910FM32X6 MCUs start at $6.99.

- Dave Busrky
EE Times




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