Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Power/Alternative Energy
Power/Alternative Energy??

Plan early to reduce IC power usage

Posted: 01 Jul 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Eike Schmidt? ChipVision? ic? power consumption? cmos logic?

Historically, area and performance have been the key drivers for IC design. But increasingly, power minimization has become the key objective, with more and more designs failing or having to be respun due to power issues. Consequently, a consistent methodology for low-power design is required right from the start of the design, taking computation, communication and storage power costs into account.

The dynamic-power consumption of CMOS logic is usually dominated by the switching of capacitive loads. This can be estimated by P = A * f * C * V2, where C is the capacitance, V is the voltage, f is the frequency and A is the number of switches per clock cycle. Power-reduction techniques have traditionally concentrated on minimizing one or several of these factors. With reduced feature size, however, leakage currents gain in importance.

The biggest improvements can be made prior to RTL design, though. Hence, the most important recommendation is to choose efforts wisely. While gate-level optimization is needed, you must ensure that all important power-related issues on global and system levels have been addressed earlier in the cycle.


  • Attack leakage early in the design flow. Leakage would appear to be a low-level issue, but the most powerful leakage-reduction techniques exploit idleness, turning off the power supply or increasing the threshold voltage during periods of inactivity. Such idle periods can best be identified at higher levels of abstraction.

  • Consider the dynamic behavior of a system early. The dynamic behavior defines a system's power characteristics. The power consumption of data paths largely depends on the correlation of the data streams that are occurring. In practice, it's driving for a simulation-capable description as early as possible.

  • Consciously trade off power for performance, area and QoS. Since dynamic power depends linearly on frequency and quadratically on voltage, first consider reducing these parameters locally as much as throughput requirements allow. This may require introducing new voltage and clock domains. You might also consider techniques like pipelining and parallelization to make up for lost performance.

  • Exploit varying workloads. It's a good idea to turn off all inactive parts of the design or to turn them into low-performance, low-power states. Clock gating has already become a common-sense low-power technique, but also consider going one step further and applying dynamic reduction of clock frequency and/or supply voltage.

  • Consider power on all levels of abstraction. Try to get a firm grip on your power issues prior to RTL, where the savings potential is much larger and design changes are much more easily implemented than later on lower levels. Keep an eye on power as you proceed through the design cycle.


  • Make it as slow as possible. This used to be cheap advice. But keeping down the speed is no longer a no-brainer because energy consumed via leakage currents depends on the length of the process activity. With leakage becoming more important, "run fast and sleep long" might be the better strategy.

  • Neglect vital parts of the system. Data path, control logic, software on processors, analog blocks, memories and buses can significantly affect the overall power budget.

  • Fly blind. Each design has its own power-critical aspects. For one design, the clock might be power-critical; for the next, it might be memory or for another, the multipliers. Don't just make assumptionsyou might be wrong.

  • Be late. The power-savings potential diminishes over time as a design gets more and more concrete. You can easily save a factor-of-several-times prior to RTL, but the same degree of power reduction will be very hard at the gate level.

  • Expect a silver bullet. As much as EDA vendors would like it, no single technique can solve the power problems for all designs. The issues are highly dependent on the design, implementation and environment.

- Eike Schmidt
ChipVision Design Systems AG

Article Comments - Plan early to reduce IC power usage
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top