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Sunplus tapes-out design with Synopsys solution

Posted: 05 Jul 2006 ?? ?Print Version ?Bookmark and Share

Keywords:tape-out? design? IC Compiler? Synopsys? Sunplus?

Synopsys Inc., a major provider of semiconductor design software, announced that Sunplus Technology Co. Ltd, a supplier of consumer ICs, has taped-out a large high-density consumer design with Synopsys' IC Compiler physical implementation solution.

According to the press release, Sunplus chose Synopsys design consultants and the IC Compiler to complete the physical layout of the design within 30 days. The challenge faced by the design team was to achieve the chip's performance target while not exceeding the tight die-size constraint. Sunplus said it achieved a utilization of close to 90 percent.

The IC Compiler and sub-flows from the Pilot Design Environment were used to achieve Sunplus' 2.5-million-gate design. Synopsys reported that IC Compiler users have consistently reported 2X faster turnaround time, on average.

This productivity boost is said to be attributed to the Extended Physical Synthesis technology that unifies optimizations across synthesis, placement, clock tree and routing. In the case of the Sunplus project, this consumer design also demanded that the die size be as small as possible. As a result, the layout was compressed to 88 percent utilization.

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