Next PCI Express to deliver 5Gbps data rate

The 2.5Gbps PCI Express interconnect is slowly shifting gears into a 2.0 version expected by the end of the year that will rev data rates to 5Gbps. Details were discussed at the PCI Special Interest Group (SIG) annual meeting in June. Generally, doubling speed in a given design means halving distance. Thus, engineers have several open questions on whether some connectors, board materials or other aspects of existing designs may have to change to accommodate the new speeds in the existing form factors.

"One of the big concerns is, can version 2.0 handle all the Express form factors? There's a whole new round of simulations going on to check that right now," said Michael Krause, an interconnect expert in Hewlett-Packard Co.'s X86 server group. The simulations may take two months, he added.

What's clear is that "all the design budgets for 2.0 will be very tight," said Ramin Neshati, a technical program manager from Intel Corp. who has worked on version 2.0 from its inception.

The 400ps jitter margin of the 2.5Gbps version 1.1 will shrink to 200ps for version 2.0. Clocks and phase-locked loops will have to handle most of the narrowing restrictions, Neshati added.

One recent proposal suggests limiting Express 2.0 implementations to 85-ohm impedance on a PCB. However, simulation tests may show that the existing 100-ohm levels are adequate, at least in some implementations.

Meanwhile, designers have identified a handful of new features they will add to the 5Gbps version. They include an access control feature that allows software to control packet routing on the interconnect and prevents hackers from spoofing and rerouting data, primarily for peer-to-peer traffic. The feature will be implemented for PCI Express chipsets, switches and multifunction devices.

Another new feature will notify software in cases where a link automatically shifts to a lower speed or width. An update to the link-training state machine for Express will let software also control the configuration and adjust the speed of Express 2.0 links.

Besides obtaining higher performance, graphics chips will use the fast channels of version 2.0 to eliminate graphics memory in favor of using the system's main memory—even when graphics are on a card, off the motherboard. However, desktop and notebook computers may implement a mix of 5Gbit Express for graphics and 2.5Gbit Express for everything else for a few product generations.

In servers, both Serial ATA and serial-attached SCSI standards are preparing a move up from 3- to 6Gbps speeds that will want Express 2.0. In addition, multiport controllers for Ethernet, Infiniband and Fibre Channel will demand the faster system link as well.

The PCI-SIG also provided an update on work on a variety of form factors for Express add-on products. Development on an Express card designed to plug into the display side of notebook computers has been suspended because engineers found they could not produce such cards at low enough costs given problems in heat, thickness of the cards and electromagnetic shielding from LCD modules.

Mini mini-card
Instead, the group has decided to define a half-size mini-card for internal use in the base of notebooks and small desktops. The card will be about 30mm wide and 26mm tall, and designed so that two of them can fit into the same area as an existing full-size mini-card. They will be mainly used for enabling last-minute build-to-order notebook configurations for Bluetooth, Wi-Fi and other wireless standards.

Separately, work on a cabled version of PCI Express is slowly moving forward. A 0.7 draft—which now includes 16x as well as 1x, 4x and 8x versions—has gone out to SIG members. The cost of the cables is still unclear.

The cables would be used to link servers in different racks, act as a fast docking connection or link separate compute and storage "bricks" in disaggregated desktop designs. It will not be clear whether the cables, rated for distances of up to 10m at 2.5Gbps, will be able to work with the 5Gbps version of Express until the basic Express 2.0 simulation work is completed.

Work continues in the SIG on I/O virtualization, which will serve both the existing 1.1 and next-generation 2.0 versions of Express. The spec, now approaching a 0.5-version draft, could be finished as early as the end of the year. It includes separate specifications for device sharing, address translation services (ATS) and both single- and multiprocessor systems.

The ATS feature will require a relatively small number of new hardware gates on both I/O endpoints and controlling processor chipsets to implement what is essentially a caching function.

Finally, SIG leaders gave a peek at the more-distant future. The group hopes to deliver another generation of Express on copper traces that could boost the 5Gbps rate of the 2.0 version 1.5 to 2.2 times before a transition to optical links.

Seeking 10Gbps
The SIG is conducting some lab work on receiver equalization and transmit pre-emphasis to find out what techniques could bring 10Gbps speeds to PC price points in any reasonable time frame.

"Everyone wants to go to smaller, narrower, faster and less power-hungry links. Keeping the power the same is a tough challenge," said Neshati. "We don't have a schedule or a name for this new generation, but it should emerge when the market is ready."

Some graphics companies have suggested that with 10Gbps links, discrete graphics products could essentially eliminate any advantage of today's CPU chipsets with integrated graphics that are very popular in mainstream PCs. Such products are likely to become drivers for the third-generation Express work, one engineer said.

Rick Merritt
EE Times