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Simulator supports Open IP Encryption design flows

Posted: 13 Jul 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Aldec? Synplicity? Open IP Encryption Initiative? Riviera 2006.06?

Aldec Inc. has announced that the new version of its Riviera simulation tool supports design flows based on the Open IP Encryption Initiative, a non-proprietary intellectual property (IP) encryption method authored by Synplicity Inc.

Lack of an industry-wide standard for IP encryption and decryption has concerned both IP vendors and their customers for a long time. With built-in support for Open IP Encryption flow, the Synplify and Synplify Pro FPGA synthesis software and Aldec's Riviera tools enable engineers to easily compile, simulate and synthesize, Verilog-encrypted IP, the company explained.

"Aldec's support for the Open IP Encryption Initiative will help create a front-to-back design capability with comprehensive encrypted IP support," said Andy Haines, senior vice president of marketing at Synplicity. "Users of Aldec's Riviera product will be among the first to benefit from a truly open and easy-to-implement IP protection scheme where all tools will be able to analyze and optimize the IP source code in the same way as unencrypted source code."

Simulation of encrypted Verilog sources based on Synplicity's Open IP Encryption Initiative is now possible with the new Riviera 2006.06 high-performance SoC simulator. The flow is compatible with the recently published Verilog standard IEEE Std 1364-2005 and forthcoming VHDL 2006 standard. It promises easy encryption of any fragments of IP cores for secure delivery from the IP vendor to the customer. The encryption involves no action on the side of the customerall required activities involve the IP vendor and tool vendors only. Customers can open delivered IP source but will only see unintelligible, encrypted and encoded text. The Riviera compiler will be able to decrypt the source on-the-fly, according to Aldec, leaving no traces that could compromise the security of encryption.

Aldec said Riviera 2006.06 also includes faster Verilog and VHDL compilation and simulation; PSL assertions embedded in VHDL code for improved verification, communication and IP correct usage detection; Expression Coverage for fine grained statistics analysis of testbench effectiveness; and numerous GUI enhancements.




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