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IBM, Chartered to support Synopsys IP for 65nm

Posted: 13 Jul 2006 ?? ?Print Version ?Bookmark and Share

Keywords:IP? intellectual property? DesignWare? IBM? Chartered?

Synopsys Inc., a major EDA provider, announced that IBM and Chartered Semiconductor Mfg have agreed to support Synopsys' DesignWare mixed-signal connectivity intellectual property (IP) on the 65nm process developed for the Common Platform technology.

As part of this agreement, Synopsys is porting PHYs for USB 2.0, PCI Express, SATA and XAUI protocols to the 65nm process technology developed by Chartered, IBM, Infineon Technologies and Samsung, and also porting the DesignWare USB 2.0 nanoPHY IP to IBM and Chartered's 90nm process node. These PHYs are analog interfaces used in current high-volume, consumer, computer, storage and networking applications.

Introduced earlier this year, the DesignWare USB 2.0 nanoPHY IP is said to offer half the power and die area compared to previous generation solutions. This product is currently available for the CMOS 9SF and CMOS 9LP 90nm processes, and will be available in Q3 2006 for the CMOS 10LP 65nm process. PCI Express, SATA and XAUI PHYs are expected be available in Q4 2006 for the CMOS 10LP 65nm process.




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