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Enigma samples out 'first' linearly scalable packet switching chipset

Posted: 19 Jul 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Enigma? HybriCore? linearly scalable packet switching chipset?

Enigma Semiconductor announced it is sampling a linearly scalable packet switching chipset, touted to be the world's first. According to the company, the chipset family, which features both packet switches and a range of fabric managers, sets new benchmarks for density, efficiency and flexibility. Based on Enigma's HybriCore architecture, the chipset promises to streamline time-to-market for OEMs designing next-generation metro access switches and routers, multi-service provisioning platforms, enterprise routers and storage platforms.

Traditional shared-memory architectures offer limited system scalability, while existing cell-based architectures are inherently inefficient. The HybriCore memoryless crossbar switches are said to address both of these challenges, scaling to support multiple-terabit configurations and switching complete packets across the backplane to eliminate segmentation and reassembly. This scalability and efficiency allows system architects to future-proof their network and communications systems by ensuring that next-generation line cards can be deployed within existing hardware infrastructure platforms, Enigma explained.

"With rising demands from both enterprise and carrier network providers, the only way to achieve the next level of switching scalability is to break the mold," said Rob Sturgill, president and CEO of Enigma. "Finally, with the release of the HybriCore chipset, system architects have a fully scalable packet-based switching system for building elegant and robust carrier and enterprise equipment to support triple play applications. These silicon building blocks support user-defined quality of service levels, ultimately ensuring a positive user experience with these value-added, revenue-generating services."

Density, efficiency and flexibility
A single HybriCore-based switch device switches up to 360Gbps of non-blocking, full duplex traffic. Multiple switch devices scale the design linearly to support multiple terabit system configurations that have not been possible with legacy switching silicon. The fabric managers, residing on the line card in a typical system topology, support 10-, 20- or 40Gbps line card configurations and can be combined to achieve higher density 80-, 120- and 160Gbps implementations. This device requires no external buffer memory, the company said, which drastically reduces PCB footprint, system power and system cost.

Legacy switch architectures typically convert packets into equal-length cells, forcing a significant amount of backplane bandwidth to be used for cell headersand in some cases, for partially empty cells. Maintaining scalability with this legacy approach requires a substantial increase in aggregate bandwidth across the backplane, increasing design complexity, power and cost. Enigma said the HybriCore chipset achieves performance and scalability by switching complete packets across the backplane, without the inefficiencies introduced by segmentation and reassembly schemes typical of legacy switching architectures. An intelligent scheduler ensures packets are transferred back-to-back across the serial links, resulting in bandwidth utilization of greater than 98 percent. The scheduler also ensures high priority packets are switched with very low latency, even when the switch is concurrently transporting large packets, explained the company.

Enigma added that it has incorporated enhanced Advanced Backplane (ABP) technology from Rambus Inc. into the HybriCore chips to provide highly robust serial links that support data rates from 2.5Gbps through 12.5Gbps. These serial links integrate equalization schemes to ensure reliable operation despite changes in temperature, voltage and humidity. The family of HybriCore chips supports a range of performance and price targets, the company said, providing design flexibility for system architects.

Mix and match
The HybriCore chipset family initially includes two packet switches and three fabric managers. These devices can be mixed and matched to allow system architects to make tradeoffs based on system power, performance and cost requirements. The EN6105 integrated switch is designed for use in small modular chassis or "pizza box" applications that demand minimal footprint, low power and low cost. The EN6110 is designed to address massively scalable network equipment architectures, with the capability to directly address up to 36 line cards.

The EN6210 Fabric Manager is a 10Gbps single chip line card solution; the EN6220 Fabric Manager is a 20Gbps single chip line card solution; and, the EN6240 is a 40Gbps single chip line card solution. No external buffer memory is required in designs based on these fabric managers, which minimizes power dissipation and PCB footprint. The EN6200-family of fabric managers incorporates industry-standard interfaces for direct connectivity to a range of network processor units, ASICs and specialty packet processing devices.

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