Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Boundary-scan tool eases FPGA, CPLD programming

Posted: 19 Jul 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Macgraigor? J-SCAN? boundary-scan tool? debugger?

For programming FPGAs, CPLDs and other devices, Macraigor Systems LLC announced the availability of J-SCAN Version 2.1 high-speed boundary-scan debug and programming tool. Macraigor Systems is a supplier of JTAG and background debug mode (BDM) applications for on-chip debugging.

Macraigor's v2.1 supports USB 2.0 and USB 1.1, with ten times improvement in performance. The technology lets you facilitate early test development, shortening development cycles and prototyping processes.

Version 2.1 of J-SCAN, communicating to a target across the USB interfaces, also supports Motorola-defined SPI flash programming, where it supports systems using FPGAs and other embedded devices.

According to Macraigor, its J-SCAN provides "significant advantages" compared to logic analyzers and oscilloscope probes. J-SCAN lets you observe the behavior of the pins under a BGA, for example, in real-time on your PC. The J-SCAN debug and programming tool also lets you manually place pins to any logic state, using point-and-click with a mouse.

You can therefore observe logic state transitions and instruction addresses sent and received across individual pins, providing visibility in debugging SoCs, integrated components and new board designs.

For the first time, IC designers now have visibility into and control of every pin. If a CPU isn't yet available and you need to program flash, doing so involves setting up signals (address, data, enables), selecting a data file, and pressing J-SCAN's PROGRAM button.

The included USB 2.0 download cable enables programming times of minutes, rather than hours or days. Utilities to program FPGAs and CPLDs are also available.

J-SCAN also works independently of any logic inside a JTAG device, so no special firmware, code, or logic needs to be installed. The J-SCAN debug and programming tool also gets you up-and-running in minutes. You plug in a Macraigor usb2Demon interface, drop any type of IC device on the screen, and press a scan button. Instantly, all activity on every boundary-scan enabled pin on any device or chain of devices is visible on your PC or laptop.

The J-SCAN manual is also written in a tutorial style that provides info on J-SCAN features and how to simulate faults, but also covers the fundamentals of boundary scan. No prior boundary-scan experience is required. Multiple J-SCAN video tutorials featuring a fully populated demonstration board are available online, too.

Already available for orders, J-SCAN is priced at about $1,900. The kit includes J-SCAN debug and programming software, a USB 2.0 interface cable, a demo board, a power supply, and a Getting Started tutorial manual.

- Alex Mendelsohn

Article Comments - Boundary-scan tool eases FPGA, CPLD ...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top