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Speedy JTAG controller priced below $10,000

Posted: 20 Jul 2006 ?? ?Print Version ?Bookmark and Share

Keywords:IEEE-1149.1? Corelis? PCIe-1149.1? PCI Express? JTAG controller?

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Meeting the needs of developers embedding IEEE-1149.1 testability, Corelis' less-than-$10,000 PCIe-1149.1 boundary-scan controller product abounds with proprietary techniques and technologies, not the least of which is PCIe speed and plug-and-play operation. These features combine to let the system operate at up to its sustained 80MHz rate.

The PCIe-1149.1 is a single-lane PCIe card, and is compatible with all compliant PCIe slots, whether they're x1, x4, x8 or x16. It's mapped to 132Mbytes of memory in the host Windows 2000 or Windows XP PC.

To implement JTAG, all your design needs is incorporation of industry-standard 10-, 16- or 20-pin test access point (TAP) connectors. The host PC needs to be able to supply 3.3V at about 1.5A to the board.

The PCIe-1149.1 is also hardware-compatible and software-compatible with Corelis' forerunner ScanPlus and Scan-Express family of IEEE-1149.1 products.

In use, the PCIe-1149 ensures a scan efficiency of 100 percent at each of up to four concurrently scanning JTAG. As such, the PCIe-1149.1 system can be used in testing and/or in-system programming (ISP) of devices and boards, and can actually be used at any level in systems that are compliant with the 1149.1 standard.

The product includes the namesake PCIe-1149.1 controller card itself, as well as an intelligent ScanTAP-4 Remote Pod. The controller card then connects to the access pod across a SCSI cable that can be as long as 30ft. The data-scanning controller is completely de-coupled from the PCI bus in this scheme.

Automatic scan delay
You also get automatic scan input signal delay compensation inserted into signal paths. Delay is used to counteract obstacles associated with the combination of high test clock (TCK) rates and remote target locations at extended distances.

Scanned patterns are distributed to the target device or devices via the ScanTAP-4 pod that contains (as its name implies) four TAPs. The pod applies test vectors and/or ISP patterns with a variety of JTAG chain topologies.

If your board under test consists of groups that include multiple devices, each with their own TAP, then the ScanTAP-4 lets test vectors be applied to each of the target TAPs individually, one TAP at a time. It can also operate jointly to include all TAPs, testing and programming four boards concurrently.

A failure on any individual board is logged. Even so, that doesn't stop the system from testing remaining target devices. This concurrent gang mode of operation offers performance increases when testing, as well as ISP, and verification of multiple targets. You can do gang testing and ISP of devices such as flash memories and CPLDs, and do that on from one to four boards.

ScanTAP pods are also available to support four, eight or 32 TAPs. Multiple ScanTAP pods can also be combined to support up to a whopping 1024 target boards.

The TAPs on remote pods also include dedicated pins on their JTAG interface connectors that can be used to detect the presence of the target board. The state of this signal can be monitored by software to detect both the presence of the target device as well as the proper insertion of the test cable.

The levels of parallel I/O (more on this in a moment), local TAP ports, and each pod TAP is also software programmable. You can set any voltage between 1.3V and 3.3V in increments of 50mV. The ports of the ScanTAP-4 can also be slew-rate adjusted.

System-wide clocking
A system-wide TCK rate for all TAP ports is also programmable. A range of TCK frequencies is made possible by the use of a PLL (phase-locked loop) clock generator. Using it, you can select any TCK rate from 390kHz out to 80MHz. You can do this with resolution increments of less than 2-percent. If you wish to feed-in an external TCK reference, a coaxial connector is available for this purpose.

Operationally, the PCIe-1149.1 controller and remote pods rely on on-board A/D converters. These A/Ds measure connected power voltages from the target, with voltages from two target levels able to be compared against user-defined limits. This provides detailed signal-voltage checks at any stage of your test plan.

Avoiding smoke tests
The Corelis PCIe-1149.1 intelligent boundary-scan controller can also automatically detect shorts on a target system. To do this, the target is not powered up, but a regulated drive current is momentarily applied to its bus. By measuring this current, you can get an approximation of load resistance. This calculation lets you know if there are any shorts, before any smoke tests are made.

Earlier, I mentioned parallel I/O. The controller card supplies 16 parallel input lines, and 16 parallel outputs, organized into two 8bit ports. The parallel outputs are implemented as three-state logic.

These parallel I/O lines ports can be used to control and sense functions in your target system that can't be controlled or observed through boundary-scan operations. These ports are especially useful for testing target systems that have components that aren't 1149.1-compliant.

You also get three bi-directional I/O signals on each port of each pod. These totem-pole or open-collector lines are also programmable.

- Alex Mendelsohn
eeProductCenter




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