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TSMC reference flow integrates Cadence platforms

Posted: 20 Jul 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Reference Flow 7.0? Encounter? IC design platform? Allegro? system interconnect platform?

Cadence Design Systems Inc. and Taiwan Semiconductor Mfg Co. (TSMC) announced the integration of the Cadence's Encounter digital IC design platform and Allegro system interconnect platform into TSMC's Reference Flow 7.0. The reference flow supports designs targeting TSMC's Nexsys 65nm process technologies.

The flow is intended to deliver a methodology to address design issues at 65nm, such as tight manufacturing parameters, increase in leakage power and new extraction requirements. Cadence said its technologies address these issues by improving concurrent routing and dual-via insertion, adding new leakage power reduction strategies, and addressing process-variation extraction issues within Reference Flow 7.0.

Reference Flow 7.0 is said to expand the range of power optimization options to include both coarse grain MTCMOS power gating and dynamic-voltage and frequency scaling. The technologies can be used to design multiple supply voltages and power domains, leakage power and de-coupling capacitance optimization, automatic power-grid generation, and dynamic voltage (IR) drop analysis with actual IC package load models.

Elements of the Encounter platform within Reference Flow 7.0 include Encounter RTL Compiler global synthesis, Encounter Test, SoC Encounter system, Cadence QRC Extraction, VoltageStorm Dynamic Gate power rail analysis, and CeltIC Nanometer Delay Calculator.

New capabilities in Reference Flow 7.0 include DRC rule routing, half-track wire spreading and critical area analysis, which analyzes wire density in a design.




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