Cadence, ARM introduce first automated design for ARM Cortex-A8

Cadence Design Systems Inc. and ARM announced the joint development of the first automated RTL design and implementation flow for the ARM Cortex-A8 processor.

According to the press release, the ARM-certified flow, called "Cadence Encounter Express Flow for the Cortex-A8 Processor," delivers an industry-leading 1,500 Dhrystone MIPS within a simple and synthesizable methodology. Chip designers can quickly deploy high-performance, power-efficient processing in next-generation mobile, consumer and other applications. The new flow also enables small teams of engineers to tape out even high-performance designs in a few months, gaining significant time-to-market and cost advantages, the companies said.

The automated design flow, based on the Cadence Encounter digital IC design platform, was jointly developed by a team of ARM, Cadence Design Services, and Cadence Encounter R&D engineers over a twelve-month period. A number of RTL synthesis, placement, timing, and clock enhancements were developed specifically around the Cortex-A8 design, and are incorporated in the latest Encounter release, shipping in production this month.

"At nanometer geometries and above 500MHz, very careful alignment of the design flow to the yield, power and physical properties of the process is mandatory. Working closely with ARM Artisan libraries and processor development teams, these factors were included in the flow," said Jan Willis, senior vice president, industry alliances at Cadence.

"The new automated flow developed in collaboration with Cadence Design Systems and certified by ARM enables our silicon Partners to implement Cortex-A8 processor-based designs quickly and efficiently, and achieve their performance and power goals," said John Cornish, vice president of marketing, processor division, ARM.