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Lithography efforts trailing 32nm target

Posted: 01 Aug 2006 ?? ?Print Version ?Bookmark and Share

Keywords:David Lammers? lithography? 32nm? VLSI Technology? The International Technology Roadmap for Semiconductors?

The chip industry is enjoying a short reprieve as immersion lithography continues Moore's Law of scaling for the next few years. But for chips with a 32nm half-pitch, lithographers are counting on either extreme ultraviolet or immersion 193nm scanners enhanced with high-index fluids. Neither option may be ready in time, forcing the industry to use onerous double-exposure and double-patterning techniques, participants said at the recent 2006 Symposium on VLSI Technology.

The International Technology Roadmap for Semiconductors defines a technology generation as the half-pitch!one half of a line-and-space pair. For the 32nm half-pitch that leading flash and MPU manufacturers will bring to market in 2012, the race to develop a manufacturing-worthy lithography system is a top priority now. Masaomi Kameyama, manager of Nikon Corp.'s lithography engineering staff, said customers need a lithography solution in hand by 2009 to develop their 32nm half-pitch technology.

If the materials issues facing both extreme ultraviolet lithography (EUVL) and high-index immersion lithography are not resolved by then, customers may be forced either to wait for a high-throughput solution or to use double-patterning and double-exposure techniques.

Double patterning requires that the exposures be done twice, first exposing half the lines, etching and performing the other steps. Then, another coating of resist is spun onto the wafer, and the other half of the pattern is exposed in the interstitials, or between the first set of lines.

The approach is expensive and slow, but technically somewhat easy, although it requires overlay accuracy of about 2nm. If the back of one's hand is taken as an example, the first and ring fingers would be printed and processed, and then the third and pinkie fingers are exposed.

Double exposure, for its part, involves exposing one set of lines and then, before other process steps are done, moving the exposure to an adjacent space and exposing the second set of lines.

While double exposure is faster than double patterning, the trick is to find a nonlinear resist!that is, a resist chemistry that can absorb weak light from the adjacent exposure without creating a pattern. The resist must have a threshold of photons, below which it does not become activated.

Nikon's Kameyama said this nonlinear resist is the "magic material" that would be required to make double-exposure techniques practical. "If we cannot develop immersion with 1.6NA lenses, then we will definitely need double-exposure lithography for the 32nm node," he said.

Many assume that a magical solution will arrive to bail out the 32nm half-pitch generation. That line of reasoning draws on the long history of extending optical lithography from one process to the next. Just as the industry realized five years ago that the 157nm wavelength faced near-fatal problems, the ability to extend 193nm lithography with immersion techniques was picked up and made workable.

Water has a refractive index of about 1.4, bending light as it moves through the thin film of liquid. As a result, scanner makers can create lenses with numerical apertures higher than 1.0, and increase the resolution and depth of field compared with "dry" lithography. Even purified water presents challenges, since it tends to dissolve the resist chemistry and create defects.

Extending immersion with a high-index fluid is proving difficult, however. Liquids with a 1.65 index of refraction have been tested; but if a workable system is to be realized, the bottom lens element, which gathers the light, must be matched with the index of the fluid, said Phil Ware, a senior fellow at Canon Inc.

"What the industry really needs for the 32nm generation is a fluid with an index of 1.8 or 2. That third-generation fluid, and the matching lens element, have not been identified and definitely are not going to be ready in time. There is no infrastructure to make that type of glass," Ware said.

While the National Institute of Standards and Technology has identified some garnets that might fill the bill, Ware said "it is not apparent that they have the right index. And they have birefringence problems!the same issue that killed the 157nm wavelength technology."

EUVL faces serious challenges, including the source of the 13.5nm radiation; optic lifetimes; defects on the reflective mask blanks; and a resist chemistry with sufficient sensitivity, resolution and line edge roughness.

"For EUVL, meeting the timing targets for the 32nm half-pitch will be difficult," Nikon's Kameyama said.

For EUVL, the defect density on the reflective masks must be improved by three orders of magnitude. Foremost among the challenges is the quality of the resists. For 193nm production systems, chip vendors now use resists with sensitivities of about 20mJ. For EUV, a resist with at least 10mJ of sensitivity!and preferably better than that!is needed, said Mike Mayberry, Intel Corp.'s director of components research.

A resist must be sensitive to photons in order to expose patterns quickly. A resist with poor sensitivity requires an increase in the source power of the light.

Over the past year, the major scanner makers!ASML, Canon and Nikon!have realized that the original target for EUVL source power!defined as the amount of 13.5nm radiation at the intermediate focus of the optical path!was set too low, given the difficulties in finding a sensitive EUVL resist. The original target of 115W of EUV source power is "almost at the point" of being revised to 180W, Kameyama said.

"The 180W target for source power can be reached, but it may be only for short-term operation," he said. "The challenge is that for manufacturing at high throughputs, we have to develop source technologies with good lifetimes and reliability."

Giang Dao, COO at International Sematech, said that lowering expectations for resist sensitivity and increasing the targets for EUVL source power are merely shifting the burden from one area to another. At a recent EUVL workshop in British Columbia, resists were rated as the No. 1 challenge for EUVL, he said.

"One scenario is to shift the burden from the resists to the source power. But in the past, whenever a new wavelength comes in, the resist makers have all made significant improvements," said Dao, an Intel assignee to Sematech.

Kameyama noted that the 248nm lithography solution was delayed for about five years: The 248nm tools were ready well before a workable 248nm resist chemistry was developed. Nikon has used a small-field-size EUVL system to create 30nm lines and spaces, but it required almost 1J of exposure energy!impractical for high-throughput scanners.

Few restrictions
The advantages of EUVL include the ability to design circuits with relatively little optical proximity correction and "very few restrictions on the patterns," Kameyama said. Also, EUVL scanners could be used initially for the 32nm half-pitch generation and then extended to further generations, spreading the high cost of the EUVL systems out over time.

Mayberry said Intel is developing EUVL and has a second program to study extensions to immersion lithography. Also, the company is working on double-patterning techniques, studying how the alignment and overlay challenges can be met. With those three options, Intel is confident it will be able to meet its targets.

"This is the year we get the full-field beta EUV systems, and then the industry can use those to do the kind of engineering work required," Mayberry said. "Right now, Intel's plan of record is to bring EUV into manufacturing in 2011. With Murphy's Law in force then, it might slip a year. We are making a lot of progress."

- David Lammers
EE Times

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