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10Gbps dual CDR rolls for short-reach XFP apps

Posted: 03 Aug 2006 ?? ?Print Version ?Bookmark and Share

Keywords:AMCC? clock data recovery? CDR?

Building on the success of its first 10Gbps dual clock data recovery (CDR) device, Applied Micro Circuits Corp. (AMCC) has developed the S19256 dual CDR for use in short-reach and intermediate reach XFP modules.

AMCC's latest CDR device is designed to reshape the signal in an XFP module, particularly in 2-40km short-reach and intermediate applications that require data to be transmitted at 10Gbps using multiple standards, including 10Gbit Ethernet, SONET/SDH, or Fibre Channel. Unlike its predecessor chip, the S19233 dual CDR for 40-80km of fiber, the S19256 is not designed with an Electronic Dispersion Compensation (EDC) function.

"This compensates for chromatic dispersion along the optical fiber and you have to design a certain amount of power to realize this function. The chip that we introduced does not have this EDC part, and is tailored for the 2km up to 40km market. And in this range you don't need to compensate for chromatic dispersion because the effects are rather small," said Oswin Schreiber, AMCC's product marketing manager for PHY products.

Consequently, AMCC is offering makers of 10GbE optical modules a device that is lower in power and cost compared with previous offerings, Schreiber said.

At less than $40 each in volume quantities, the S19256 is priced 30 percent lower than the S19233. Power dissipation is about half-a-watt compared with 650W. Packaged in a 6-by-6mm2 PBGA, the S19256's small footprint is compatible with the S19233.

"The footprint is the same [for both the short-reach and long-reach markets] so if a customer designs a module for one of the applications, it's very simple to switch to a different application," Schreiber said. "What an XFP module manufacturer has to do is only replace the optical part of it, which is the most costly component of the system," he said.

When building an XFP module, a lot of attention has to be paid to the optical side of the dual CDR. AMCC designed its device with a built-in equalizer to mitigate data-dependent jitter generated during the transmission of signals in FR-4 material and equalize for any losses when an electrical signal is transmitted into a line card.

"The bottom line benefit is performance is greatly improved if you compensate for data-dependent jitter generated traveling over the FR-4 material from your ASIC, from your SerDes into the XFP module," he said.

Another one of the S19256's key features is high cross-talk isolation. The PHY chip runs two 10Gbit data streams with no disturbing crosstalk, and can be connected on the motherboard to AMCC's 10Gbit SerDes devices, including the S19235 and S19237.

The optical receiver of the S19256 integrates an AGC amplifier with offset cancellation circuitry with the CDR function. The transmit electrical side of this device also has an equalization circuit and CDR that reshapes the data after up to 20inches of transmission over copper on FR-4 PWB material, with low jitter generation of 25 mUI. The low-jitter CML interface is designed to be compliant with the bit error rate requirements of the Telcordia and ITU-T standards.

The device is already sampling; production will start in September.

- Ismini Scouras

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