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Cadence introduces line of reusable verification IP

Posted: 11 Aug 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Cadence? universal verification components? UVC? verification IP? VIP?

Cadence Design Systems Inc. recently introduced the Universal Verification Components (UVCs), a new line of reusable verification IP (VIP) that integrates compliance management and mixed-language flexibility with advanced simulation-based testbench technology. UVCs, part of the company's strategy to deliver VIP that spans the entire verification process, promise to maximize quality, predictability and efficiency, while minimizing schedule delay risks and the need for specific protocol expertise.

According to Cadence, the new verification component IP includes a unique executable verification plan (vPlan) that drives management of the verification process and automatically calibrates, measures and reports on protocol compliance. In addition, UVCs are said to be the industry's only VIP that supports all standard languages backed by the IEEE, including SystemVerilog and "e" for test benches, and SystemC, VHDL and SystemVerilog for design.

Cadence will provide UVCs for protocols most in demand by customers including ARM's AMBA AHB and AXI, PCI Express, Ethernet and USB. UVCs expand the existing Cadence portfolio of testbench verification IP. Each UVC is pre-verified against the protocol specifications and is based on the Cadence Plan-to-Closure Methodology for plug-and-play adoption. Users employing this VIP will gain access to its underlying integrated methodology that promises to shorten bring-up and simplify reuse of their verification environments at the block, chip and system levels, Cadance said. With this mix of powerful technology, methodology and process automation-based capabilities, the company said UVCs will provide a robust multilanguage solution that offer benefits for every design or verification specialist.

"We've seen tremendous success from thousands of customer projects using our pre-verified verification components," said Steve Glaser, corporate VP of Cadence Verification Division. "We're leveraging our proven expertise to deliver the next-generation multilanguage UVCs to bring our customers from plan to verification closure faster than ever."

UVCs are already in customer use today and will become more broadly available in Q3 2006.

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