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EDA/IP??

ESL solution prevents bug at the source

Posted: 16 Aug 2006 ?? ?Print Version ?Bookmark and Share

Keywords:MataiTech? Nauet? ESL design tool? XX? XX?

Engineers at IC design services firm MataiTech LLC could not afford commercial ESL design tools, so they built their own. Now they're rolling out Nauet, a tool that lets hardware and software engineers collaborate at the earliest stages of a design.

Starting at just under $1,000, Nauet takes in Spirit XML files or drawings from a component editor and then generates outputs for hardware and software design. The initial version, available now, provides Verilog and VHDL register headers, design documentation, a C/C++ hardware abstraction layer (HAL), C/C++ register and memory tests, and SystemC models and registers.

An enhanced version, slated for late 2006, will also provide HDL code for muxes and buses, hardware/software co-simulation, load balancing for CPUs, timed SystemC models, and a multicore scheduler and RTOS. MataiTech also plans to offer Verilog-to-C/C++ and VHDL-to-Verilog translators.

"We're allowing people to do real software development and test, and co-simulate with the hardware," said Aaron Baranoff, VP of engineering at MataiTech. "The software person can start doing coding from day one, after you've entered some basic information."

MataiTech's six engineers have been doing hardware and software development work for the past two years, Baranoff said. The team has designed ASICs, FPGAs and intellectual property (IP), and has developed both hardware and software for embedded networking projects. "As a small contract company, we found a lot of EDA tools were way out of our price range," Baranoff said.

So Baranoff and Erik Jessen, MataiTech's president, developed Nauet on their own, and the company started using it internally. Customers suggested MataiTech should sell the tool externally, Baranoff said. MataiTech developed a GUI and front end to the tool that is more friendly to external users.

"My initial background was in embedded software, and I found that most companies work in a serial fashion," Baranoff said. "First you do a chip, then you let the software folks work in it. By definition, the software is behind schedule, and if you find a bug, it's too late." Nauet lets software developers start coding early and thus is billed as an EDA tool that prevents bugs at the source.

There are many ESL tools on the market, but MataiTech believes it has a new approach. "We're very much oriented to the software person as well as the hardware person, plus we're placing it in a whole different price range," Baranoff said. "With an introductory price of just below $1,000, we're one or two orders of magnitude below the other folks."

Input to Nauet is an XML file in the Spirit IP Xact format. This file defines modules, registers, fields, memory information and timing, although the initial version of Nauet sticks to untimed models. Nauet also provides a component editor with a GUI. Information entered in that editor is saved in a Spirit XML file.

For hardware designers, the initial version of Nauet generates Verilog and VHDL register headers. The enhanced version will generate synthesizable HDL code for muxes and buses. It won't generate code for a CPU, but it will wire up an existing CPU and create address and data multiplexers.

For both hardware and software people, the initial version of Nauet produces design documentation "down to the register, bit and field level, which is all the stuff that traditionally is very human-intensive and error-prone," Baranoff said. The enhanced version will support hardware/software co-simulation with third-party HDL simulators.

The enhanced version will also analyze software/hardware interaction and help with load balancing. "We can tell you how busy you're keeping your CPU, and once we do that we can shuffle software from one CPU to another, or suggest that you make the bus width wider," Baranoff said.

The HAL generated by the initial version of Nauet includes functions or macros that allow access to individual registers and fields. Nauet also produces register and memory tests for every register defined in the system. While the initial version produces untimed SystemC models of registers, the enhanced version will add timed models. The enhanced version will also generate a "lightweight" RTOS that works across multiple CPUs. Automatic conversion utilities from Verilog to C++ and from VHDL to Verilog will also be part of the enhanced version.

The initial version is available now for $949. Baranoff said MataiTech will probably offer an "inter- mediate" version before the fully enhanced offering debuts at the end of this year, priced at around $6,000.

- Richard Goering
EE Times




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