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Realtek, Cadence collaborate on formal verification design

Posted: 18 Aug 2006 ?? ?Print Version ?Bookmark and Share

Keywords:CDNS? Cadence Design? Realtek? Cadence Encounter Conformal Technologies? formal verification?

Cadence Design Systems Inc. and Realtek Semiconductor Corp. have collaborated to reduce the risk of functional errors on its pilot multi-supply voltage (MSV) design. Realtek, a leading IC design house in Taiwan, adopted Cadence Encounter Conformal Low Power and Encounter Conformal Constraint Designer to reduce verification risks.

The Cadence product-segmentation strategy provided Realtek with multiple levels of technology tailored to specific levels of design complexity. Realtek used Encounter Conformal Low Power to perform functional and structural checks to find critical bugs introduced during low-power implementation. Encounter Conformal Constraint Designer helped Realtek ensure constraint quality by detecting inconsistent and conflict timing exceptions early in the design process, and to perform constraint validation to achieve faster timing closure.

"Encounter Conformal Low Power reported critical bugs in power connections after place-and-route that our designers were then able to confirm and address. Encounter Conformal Constraint Designer provided a complete verification solution to help our engineers solve a difficult constraint problem," said Jessy Chen, executive vice president and spokesman for Realtek.

Encounter Conformal Low Power enables designers to verify and debug multimillion-gate designs optimized for low power. It combines low-power structural and functional checks with world-class equivalence checking to provide superior performance, capacity and ease of use. Encounter Conformal Constraint Designer automates constraint validation, generation, and refinement to ensure timing constraints are valid throughout the design process and help designers achieve rapid timing closure.




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