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IP core speeds design of Interlaken-based networks

Posted: 21 Aug 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Altera? Sarance? Cortina? Interlaken? IP core?

Three major electronics firmsAltera Corp., Sarance Technologies and Cortina Systemshave teamed up to develop the first FPGA-based Interlaken IP core aimed at accelerating the design of network systems applying the emerging protocol.

The IP core has been developed by Sarance for easy integration in Altera's Quartus II design flow, yielding the first Interlaken implementation in hardware. The Interlaken protocol IP core enables designers in the communication and storage network equipment sectors employ the interconnect specification using Altera's Stratix II GX FPGAs.

"On the internal side of the core, we're using the standard Atlantic bus interface, which is Altera's protocol within FPGA buses," said Farhad Shafai, VP for R&D, Sarance Technologies. "This allows customers to easily use our core along with any other core that Altera may have a build a full solution out of it."

The Interlaken protocol is a royalty-free specification that builds on the logical structure of SPI-4.2, or System Packet Interface Level 4 interface technology, that is widely deployed in networking equipment. Jointly developed by Cortina and Cisco systems, the Interlaken protocol is more robust than SPI-4.2, providing better error checking and data integrity.

Interlaken is also a more scalable protocol; SPI-4.2 doesn't scale beyond 10Gbps. Interlaken allows use of the latest 6Gbps serial technology in configurable increments, allowing designers to build interfaces that support 20-40Gbps applications as well as systems that will run at 100Gbps and beyond in the future.

"The benefit of Interlaken over SPI-4.2 is a 90 percent reduction in pin count. That translates into lower cost on the board and lower cost on the chips. The 90 percent reduction in pin count is one big advantage. Another big advantage is scalability. The same interface and the same protocol can be used anywhere in between 10- to 40- to 100Gbps," said Fred Olsson, product manager, Cortina Systems.

Interlaken uses SerDes technology to garner more bandwidth. The built-in SerDes blocks in the StratiX II GX FPGAs are capable of running up to 6.375Gbps, which the core can handle with ease. The lanes are programmable and can scale the protocol up to a higher bandwidth by simply adding more lanesthe core doesn't need to change.

In the middle of the core is logic that sits in front and behind the SerDes that's replicated per lane. On the right side of the core is the protocol layer TX striping and RX de-striping. Depending on what bandwidth is required, the bus that faces the FPGA is between 64bits to 256bits for 10Gbps up to 40Gbps, respectively. There's an optional test interface that allows the designer to inject expected errors in the protocol and into each lane for testing of the circuitry in the FPGA and the other device that's connected to it.

"We're using the SerDes at the maximum rate of 6.375. That reduces the number of lanes, so it gives you the lowest power and footprint. Compared with SPI, you only need two serial links running at 6.375 for a 10Gbps solution," said Shafai.

The core for 10Gbps interconnect designs uses 5,000 LUTs and 50Kits of memory, the 24Gbps core uses 11,000 LUTs and 100Kbits of memory, and the 40Gbps core uses 25,000 LUTs with 150Kbits of memory. The SPI-4.2 core with a 10Gbps bandwidth uses 4,000 LUTs and 100Kbits of memory.

"For a 10Gbps design, the Interlaken core is slightly bigger but gives [the designer] scalability and robustness," Shafai said.

Pricing is based on a standard IP licensing model. Per project, the price for the 10Gbps core is $17,500, the 24Gbps core is $25,000 and the 40Gbps is $37,500. The 10Gbps and 24Gbps cores will be available August 31; the 40Gbps core will be available Q3 of this year.

- Ismini Scouras
eeProductCenter




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