New dice interconnects support up to 100Gbps

NEC Electronics has a wafer-level packaging technology that it says permits more than 1,000 3D interconnections between the logic and memory dice used in an image-processing system.

The connections can support transmissions of up to 100Gbps, with reduced power consumption, the company claims.

The approach may be used in high-end cellular phones, videogames or digital television, said Steven Kawamoto, director of the custom SoC strategic business unit at NEC Electronics America Inc.

Following reliability tests, the technology is expected to be rolled out in Q1 2007, NEC managers said.

The system-in-package (SiP) approach is called Smafti, for "smart connection with feedthrough interposer." It uses a 7?m-thick polymide dielectric layer and copper interconnects 15?m wide to build up trace routing to an interposer layer, creating vertical interconnects with a 50?m-pitch.

A plastic compound encapsulates the package. Typical size is 15mm on a side.

Smafti uses an interposer that eliminates thermal mismatch between the memory and logic dice, said Han Park, senior engineering manager at NEC Electronics America. The dice are probed at the wafer level and attached to the interposer. A proprietary screening step ensures the maximum number of known good dice.

The approach creates wafer-level wiring using lithographic patterning and a semi-additive process. Dice are attached to the wires and encapsulated, and the rest of the silicon wafer is removed with a technique that NEC is not ready to disclose, said Park. Then the second chip is attached to the interposer.

BGAs are used to connect the finished package to the system board at 500?m spacings.

The company expects to use the Smafti approach for internal products targeted at NEC's own 3G cellphone business group, as well as to external customers, said Kawamoto.

- David Lammers
EE Times