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Hot Chips conference showcases high-performance architectures

Posted: 23 Aug 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Intel? ARM? Sun Microsystems? multicore? parallel processor?

The 18th annual Hot Chips conference held this week at Stanford University in Palo Alto, California featured presentations on the latest multicore solutions for servers and workstations and highly parallel processors for embedded applications.

Greg Grohoski, a distinguished engineer at Sun Microsystems Inc., detailed the improvements Sun will make in its next-generation Niagara 2 processor. The chip will deliver double the performance of the original Niagara, thanks to modifications that change the internal pipeline and double the number of threads running on each of the eight processor cores, Grohoski said.

Meanwhile, Intel Corp. offered a first look at the Tulsa processor-a dual-core Xeon-family chip with a large shared cache. Intel's Jeffrey Gilbert, Stephan Hunt, Daniel Gunadi and Ganapati Srinivasa detailed the inner workings of the Blackford motherboard chipset, which supports dual-processor CPUs for servers and workstations. In a third Intel paper, Jack Doweck detailed the new Core microarchitecture.

ARM Ltd discussed the Cortex-A8 1-GHz superscalar core and the clockless ARM996HS. The clockless logic design minimizes peak current and electromagnetic emissions, according to the developers. Clockless designs also tend to be robust against variations in current, voltage and temperature. That allows the ARM996HS, jointly developed by ARM and Handshake Solutions, to target applications such as portable consumer gear, automotive applications, medical implants, sensor nets, smart cards and security products.

Reconfigurable logic
Architects from Xilinx Inc. gave tip details of the Virtex 5, a next-generation FPGA architecture that lets designers craft system solutions containing highly parallel computational arrays or multiple processors configured in the logic fabric. Toshiba described a dynamically reconfigurable processor that optimizes and thereby accelerates the computations needed for multimedia applications.

Ambric Inc.'s Mike Butts and Anthony Mark Jones unveiled a massively parallel multiple-instruction, multiple-data compute fabric said to deliver throughput in the tera-operations/second range. The architecture is initially aimed at high-performance, streaming-data/control and signal-processing applications for both embedded systems and PC-acceleration cards. The configurable architecture can typically be used to replace high-end DSPs and FPGAs.

Connex Technology showcased its CA1024, a fully programmable SoC for media processing. And researchers from the University of California at Davis described an asynchronous array of simple processors.

In memory and storage, Toshiba delved into the technology behind the 0.85-inch hard-disk drive it released last year, while Innovative Silicon discussed the implementation of an ultradense DRAM that eliminates the storage capacitors by using the floating-body effect of its silicon-on-insulator structure to hold the data.

- Dave Bursky
EE Times

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