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EDA to grow faster than IC market, says analyst

Posted: 28 Aug 2006 ?? ?Print Version ?Bookmark and Share

Keywords:EDA? IC design? Intel? Zenasis? 65nm?

The increase in IC design cost and the size of design teams at the 65nm node present an opportunity for EDA, which can increase its growth rate if it can provide more productive solutions that enable customers to do 65nm designs without the need to continually increase headcount, reported Handel Jones, CEO of International Business Strategies Inc.

"What the EDA industry has to do is look at headcounts of design teams, then look at how you slow down the increase in headcount or reduce headcount through providing more productive tools," Jones said.

Jones believes the EDA market is poised to outgrow the IC industry. In 1996, he said, R&D expenditures for semiconductor companies were roughly 5.5 percent of revenues. By 2010, he said, product R&D will be almost 14 percent of revenue, with some companies spending as much as 20 to 25 percent. "Companies can't keep increasing R&D," Jones said. "They have got to make engineers more productive. The way you do that is increasing the tool productivity."

Additionally, he believes that 65nm wafer volumes are going to be ramping a lot faster than originally thought, with chip makers employing techniques like voltage islands and back biasing to manage leakage current. Companies have shown willingness to make "significant compromises" to achieve higher gate density at 65nm, including compromises in chip area and performance, as well as migration to multicore architectures, Jones said.

Jones sees leakage current emerging as the top problem facing chip designers at 65nm. His beliefs are consistent with a recent EE Times survey, which found that chip designers are currently most concerned about functional verification and timing closure, but that, as feature sizes shrink, they expect that managing leakage current will become their biggest concern.

"We think a complete new series of tools and environments will emerge [to address this area]," Jones said. "This is a whole new set of variableshow you do tradeoff current and frequency? How you do those tradeoffs is something that should be done at very beginning, not at the back end. This is a complete change."

One of the companies focused on this area is Zenasis Technologies. Zenasis employs a patented "hybrid optimization" technology to analyze designs at the logic, physical and transistor levels.

According to Dennis Harmon, Zenasis president and CEO, companies are grappling with tradeoff decisions to alleviate the leakage current problem at 65nm and even at higher nodes. "But you don't improve leakage power at the expense of frequency," Harmon said. "I would say, no matter what design node you are at, you are worried about operating frequency. Nobody wants things to run slow. People will always want things to run faster."

A different relationship with EDA
Jones said the in inefficiencies in 65nm design, including increase in area and cost, as well as achieving slower performance speed than chip makers hoped will "make IC vendors say, 'we need better tools and a different relationship with EDA industry.'"

Design cost, while typically varying by type of design, is increasing at 65nm, with larger project teams, Jones said. He estimates that project management is making up 20 to 25 percent of design cost at 65nm, up from 12 to 15 percent at 90nm.

Jones also noted that there are wide variations in what is being referred to as 65nm designs. Flash memory makers, for example, classify the technology node of a product by measuring the half-pitch of a feature size, which is far more aggressive than the more conservative methods used by Intel Corp. and other logic makers.

"Intel is probably 12-18 months ahead of the rest of the industry in production technology, if you compare apples to apples," he said. Jones also estimates that there were 41 65nm design starts in 2005. He projects there will be 127 65nm design starts this year and another 239 in 2007

Some of these design starts include test chips, Jones said, as opposed to real products. "You have right now ramping in terms of potential volume between 30 and 40 designs," he said. "By the end of the year there will be about 60 to 70 designs."

He pointed out that the high design costs at 65nm are partially a product of the fact that it is very early in the design node. Jones expects some costs to fall, but not as far as they have fallen at previous nodes. "We have seen some costs falling, but the amount of verification that you have to do is pretty extensive. We've seen verification costs per design rise dramatically."

At 90nm, Jones said, a number of companies were content to get first silicon as quickly as possible knowing that they would more than likely have to do a re-spin. At 65nm, companies do not want to go through that.

Harmon said Zenasis' ZenTime tools can help customers improve the time it takes to hit frequency targets, something he notes that they do not have the luxury of spending months on.

"Once the world has moved to this mobile device world, now you have to focus on making the tradeoff between frequency and power," Harmon said. "When you move to 65nm and below, it's not just the static, or 'on' power, that matters."

Companies are employing a variety of techniques to combat leakage power problems, Harmon said, including multi-voltage-threshold designs, as well as voltage islands and back biasing. "You name it, they are going to try it," he said.

- Dylan McGrath
EE Times




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