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Xilinx upgrades PlanAhead 8.2 analysis software

Posted: 30 Aug 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Xilinx? 65nm? FPGA? PlanAhead? Virtex-5?

Xilinx took the wraps off the 8.2 version of its PlanAhead hierarchical design and analysis software with support for its newest Virtex-5 LX family of 65nm FPGAs.

Used in conjunction with the company's Integrated Software Environment (ISE) design tools, PlanAhead 8.2 software delivers a two-speed grade performance and cost advantage over competing offerings, according to Xilinx.

PlanAhead 8.2 leverages the Virtex-5 LX ExpressFabric technology, 550MHz DSP48E slices and flexible clock management tiles, as well as accurate signal integrity analysis capability and improved graphical interface that allows designers to evaluate multiple design implementation strategies for timing closure, Xilinx said.

The tool also provides functionality to check limits for weighted average simultaneous switching output analysis, enabling designers to limit the amount of ground bounce present immediately at the output of the FPGA and prevent corruption of the operation of other devices driven by the FPGA.

PlanAhead 8.2 extends the capabilities of the ExploreAhead design exploration utility to allow users to run multiple implementations with different floorplans of their design to achieve optimal results. Xilinx added that the ExploreAhead tool offers improved directory management, process management, and integration with the FPGA bitstream generation application in the ISE environment.

Other PlanAhead 8.2 enhancements include improved management of physical constraints and viewing of the I/O pin properties for a much more streamlined design exploration and floorplanning environment, according to Xilinx.

PlanAhead 8.2 is available on all major operating systems as an option to the Xilinx ISE design suite. Single-user licenses start at $5,995, including training.

- Dylan McGrath
EE Times

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