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Toshiba tapeouts 90nm IC with Synopsys compiler

Posted: 30 Aug 2006 ?? ?Print Version ?Bookmark and Share

Keywords:SNPS? Synopsys? Toshiba? chip complier? TC90515XBG?

Synopsys Inc. announced that Toshiba Corp. has used the Synopsys IC Compiler physical implementation solution to tape out its next-generation TC90515XBG home digital network chip.

According to Synopsys, the ability to use IC Compiler to concurrently optimize the design across all five of its operating modes was a critical factor in Toshiba meeting its aggressive performance goals. IC Compiler was also able to significantly speed Toshiba's time-to-results due to its unified user environment for all design steps from prototype floorplanning through final chip finishing, the press release from Cadence said.

Compared to its predecessor, the TC90515XBG delivers higher performance and increased functionality with reduced die-size and lower power consumption. The TC90515XBG is a 90nm, high-performance wireless chip for consumer networks. It has a dual MeP core architecture that supports all IEEE 802.11 wireless LAN standards; MPEG-2 TS, PCI, I2C and Infra-Red interfaces; and content protection with DTCP-IP.

"IC Compiler and the Galaxy platform allowed us to significantly accelerate our time to results," said Takashi Yoshimori, technology executive of SoC Design, Semiconductor Co., Toshiba. "IC Compiler gave our designers a comprehensive solution for physical design with one set of libraries and constraints, a single-user environment, and support for physical test and power optimization. In addition, we found the tight correlation to sign-off with PrimeTime SI to be a key contributor to faster design closure."

Toshiba shared that they were able to achieve greater than 80 percent area utilization, power-network voltage drop of less than 25mV and more than 80 percent low-leakage cells for improved leakage-power dissipation.

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