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Fujitsu unveils three new macros for ASIC designs

Posted: 31 Aug 2006 ?? ?Print Version ?Bookmark and Share

Keywords:Fujitsu? ASICs? macro? storage interface? clock data recovery transceiver?

Fujitsu Microelectronics America Inc. has introduced a trio of new macros for custom ASIC designs. The new macros include Fujitsu's Serial ATA PHY storage interface, a 10Gbps clock data recovery transceiver and a serdes macro that is compliant with PCI Express version 1.0a, Fujitsu said. All three macros can be used in designs built using Fujitsu's 110nm process technology, according to the company.

The PCI Express serdes and Serial ATA macros have also been designed for use in 90nm designs, Fujitsu said. All three macros can be applied in customer-owned tooling and ASIC designs, the company said.

"The Serial ATA macro lets users design for storage and server applications using proven technology, while the PCI Express core delivers the very high bandwidth, excellent quality of service, and reduced power requirements that are essential for new server, desktop and other computing models today," said Jason So, senior director of Fujitsu's custom LSI business group, in a statement.

The Serial ATA macro consists of a PHY-control block, PHY core block and PHY I/O block, Fujitsu said. The 10G macro includes a differential PCML transmitter, reference clock input for PLL, with an LVDS interface, OC-192 jitter tolerance mask and synchronous data-transfer capability using CDR, according to the company. The PCI Express macro supports data rates from 2.5Gbps to 3.25Gbps, Fujitsu said, and is aimed at applications that require higher bandwidth and lower power consumption than predecessor designs using the PCI standard.

- Dylan McGrath
EE Times




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