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Restricted design rules challenge DFM

Posted: 01 Sep 2006 ?? ?Print Version ?Bookmark and Share

Keywords:EDA? DFM? RDR? 45nm? DFM tool?

July's Design Automation Conference made it clear that the EDA industry is counting on design-for-manufacturability (DFM) for a much-needed boost. But the restricted design rules (RDRs) that are quietly emerging for 45nm and smaller geometries may reduce the need for some DFM tools and techniques, some observers say.

The RDR concept is surfacing from universities and IDM research labs, and appears headed for a prominent role at 45nm and below. The idea is to enhance manufacturability by restricting the layouts designers produce. The compelling argument is that creating design layouts using only regular features will improve lithographic printability and make resolution enhancement technology easier to implement.

But very regular structures also carry potential area and performance penalties, causing some to argue that "extreme" RDRs, such as single-pitch, single-orientation rules, are unlikely to be adopted.

Most observers agree that some level of restriction seems inevitable. "All fabs are pursuing some form of RDRs at 45nm," said John Lee, general manager of the physical-verification business unit at Magma Design Automation Inc. "Not all are equally restrictive, but all enforce regularity."

"RDRs are the dirty secret that DFM companies do not talk about because strong RDRs may obviate the need for DFM," said Magma's Lee. The right solution, he said, is to augment RDRs with a physical-implementation system that includes lithography models, statistical timing and power, and correction and signoff with a physical-design tool.

Complementary rules
Most observers see RDRs and DFM as largely complementary. That's the case at IBM, which has done much of the pioneering work in this area.

"RDRs do not eliminate the need for the model-based DFM techniques currently being discussed in the EDA industry," said Paul Farrar, VP of process development at IBM's Semiconductor Research and Development Center. "When properly implemented, RDRs, in conjunction with model-based DFM, can simultaneously maintain design efficiency, schedule integrity and manufacturability. We have shown this on a leading-edge, high-performance 65nm product."

As professor of computer science and engineering at the University of California at San Diego (UCSD), Andrew Kahng has published research on RDRs. And as CTO of DFM startup Blaze DFM Inc., Kahng does not believe that RDRs will make DFM unnecessary.

"Some aspects of DFM, such as closing the loop back from lithography simulation to device-level simulation, may become less critical," he said. "Other types of variabilityreticle- and wafer-level biases, or misalignment distributions, for examplewill remain a concern."

Predictably, executives from major EDA vendors downplayed the potential for RDRs to wipe out the DFM market.

"While we see RDRs as a way to mitigate manufacturing issues, they are only one component and will certainly not lessen the need for a comprehensive DFM approach," said Srinivas Raghvendra, senior director of DFM solutions at Synopsys Inc.

Ted Vucurevich, CTO at Cadence Design Systems Inc., cautioned that RDRs are not a done deal. "This is one approach, presuming that lithographic processes do not change significantly as we get down to 32nm or 22nm," he said. "If there's a change or improvement in the lithographic process, I don't see RDRs as a direction we'll necessarily take."

RDRs are just another element in the "bag of tricks" for dealing with manufacturability issues, said Wally Rhines, Mentor Graphics CEO. "There will be more DFM in every process generation, independently of what happens with other design approaches," Rhines said.

From scorn to acceptance
The future did not always look so bright for RDRs and related methodologies that emphasize regular structures. Larry Pileggi, Tanoto professor of electrical and computer engineering at Carnegie Mellon University and director of the school's Center for Silicon System Implementation, has been conducting research on chip design using regular features since 1997 as part of a project for the university-based Microelectronics Advanced Research Corp. Back then, Pileggi said, some of the research group's member companies were perplexed about the point of the research.

But times have changed. Pileggi said he and his team have done research that proves the concept of regular design features at 65nm with no area or performance penalty by changing the way synthesis is done and the way logic circuits are configured.

Everybody was thinking that if you 'go regular', you have to pay a penalty," Pileggi said. "Nobody wants to pay that penalty until you have to. That's what we've shownthat you can do it without paying that penalty."

Kahng co-authored a technical paper on RDR trade-offs in 2004. The paper was part of a Semiconductor Research Corp. project jointly conducted with the UCSD and the University of Michigan, with collaboration from Luigi Capodieci, principal member of the technical staff from Advanced Micro Devices Inc.

The research had focused on four RDRs, Kahng said. One was avoidance of bent gates, which is generally prohibited these days. The others involved design rules for poly-to-poly minimum spacing, line-end extension and poly-to-diffusion minimum spacing.

The paper found that small increases in the minimum allowable polysilicon line-end extension can provide high levels of immunity to lithographic defocus conditions. The authors had also found that modifying the minimum field polysilicon-to-diffusion spacing could provide better manufacturability.

The authors demonstrated data volume reductions of 20 percent to 30 percent relative to a baseline "flexible" rule set, and reductions of nearly 50 percent in worst-case edge placement errors, from that set of basic RDRs. They reported that the penalty was only 0 percent to 5 percent in area and "a few percent in delay at most."

Others agree the penalties aren't large. "The expected drawback is that devices will be larger and there will be a performance hit," said Gary Smith, chief EDA analyst at Gartner Dataquest. "But chipmakers can't run these chips as fast as they want to, anyway, because of heat dissipation."

Cadence's Vucurevich said there probably won't be an area or performance penalty, as long as the RDRs apply to the device layers. "If you start talking about RDR patterns for interconnect, all bets are off," the Cadence CTO said.

"Anytime you try to take away freedom from the designers, they are going to rebel," said Pileggi of Carnegie Mellon. "But I don't think that it's really true that moving to regular features stifles creativity. The design freedom is moving to a different level, and designers will need to find different ways to be creative."

- Richard Goering, Dylan McGrath
EE Times

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